參數(shù)資料
型號(hào)： LXT384BE
元件分類： 通信、網(wǎng)絡(luò)模塊及開發(fā)工具
英文描述： Telecomm/Datacomm
中文描述： 電信/數(shù)據(jù)通信
文件頁數(shù)： 4/80頁
文件大小： 1112K
代理商： LXT384BE
LXT384 —
Octal T1/E1/J1 Line Interface Unit
4
Datasheet
4.3
4.4
TAP Controller.....................................................................................................46
JTAG Register Description..................................................................................48
4.4.1
Boundary Scan Register (BSR)..............................................................49
4.4.2
Analog Port Scan Register (ASR)..........................................................52
4.4.3
Device Identification Register (IDR).......................................................53
4.4.4
Bypass Register (BYR) ..........................................................................53
4.4.5
Instruction Register (IR) .........................................................................53
5.0
Test Specifications...........................................................................................................54
5.1
Recommendations and Specifications................................................................76
6.0
Mechanical Specifications................................................................................................78
Figures
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LXT384 Detailed Block Diagram...........................................................................7
LXT384 Detailed Block Diagram...........................................................................8
LXT384 Low-Profile Quad Flate Package (LQFP) 144-Pin Assignments and Pack-
age Markings9
LXT384 Plastic Ball Grid Array (PBGA) Package Pin Assignments ...................10
50% AMI Encoding..............................................................................................26
External Transmit/Receive Line Circuitry............................................................29
Jitter Attenuator Loop..........................................................................................31
Analog Loopback ................................................................................................31
Digital Loopback..................................................................................................32
Remote Loopback...............................................................................................32
TAOS Data Path .................................................................................................33
TAOS with Digital Loopback ...............................................................................33
TAOS with Analog Loopback..............................................................................33
Serial Host Mode Timing.....................................................................................38
JTAG Architecture...............................................................................................46
JTAG State Diagram...........................................................................................48
Analog Test Port Application...............................................................................53
Transmit Clock Timing Diagram..........................................................................61
Receive Clock Timing Diagram...........................................................................62
JTAG Timing .......................................................................................................63
Non-Multiplexed Intel Mode Read Timing...........................................................64
Multiplexed Intel Mode Read Timing...................................................................64
Non-Multiplexed Intel Mode Write Timing ...........................................................66
Multiplexed Intel Mode Write Timing...................................................................66
Non-Multiplexed Motorola Mode Read Timing....................................................68
Multiplexed Motorola Mode Read Timing............................................................68
Non-Multiplexed Motorola Mode Write Timing....................................................69
Multiplexed Motorola Mode Write Timing............................................................70
Serial Input Timing ..............................................................................................71
Serial Output Timing ...........................................................................................71
E1, G.703 Mask Templates.................................................................................72
T1, T1.102 Mask Templates ...............................................................................73
LXT384 Jitter Tolerance Performance ................................................................74
LXT384 Jitter Transfer Performance...................................................................75
LXT384 Output Jitter for CTR12/13 Applications................................................76
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相關(guān)PDF資料
PDF描述
LXT384LE Telecomm/Datacomm
LXT386BE PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|BGA|160PIN|PLASTIC
LXT386LE PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC
LXT388LE PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC
LXT400JE Hermetically Sealed, 3.3V, High Speed, High CMR, Logic Gate Optocoupler
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LXT384LE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm
LXT386 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:QUAD T1/E1/J1 Transceiver
LXT386BE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|BGA|160PIN|PLASTIC
LXT386LE 制造商:LEVEL1 功能描述:
LXT388LE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC
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