參數(shù)資料
型號(hào): LXT384BE
元件分類: 通信、網(wǎng)絡(luò)模塊及開發(fā)工具
英文描述: Telecomm/Datacomm
中文描述: 電信/數(shù)據(jù)通信
文件頁數(shù): 46/80頁
文件大小: 1112K
代理商: LXT384BE
LXT384
Octal T1/E1/J1 Transceiver
46
Datasheet
4.3
TAP Controller
The TAP controller is a 16 state synchronous state machine controlled by the TMS input and
clocked by TCK (see
Figure 16
).The TAP controls whether the LXT384 is in reset mode, receiving
an instruction, receiving data, transmitting data or in an idle state.
Table 30
describes in detail each
of the states represented in
Figure 16
.
Figure 15. JTAG Architecture
MUX
TDO
TAP
Controller
TCK
TMS
TRST
TDI
Boundry Scan Data Register
BSR
Analog Port Scan Register
ASR
Device Identification Register
IDR
Bypass Register
BYR
Instruction Register
IR
Table 30. TAP State Description (Sheet 1 of 2)
State
Description
Test Logic Reset
In this state the test logic is disabled. The device is set to normal operation mode. While in
this state, the instruction register is set to the ICODE instruction.
Run -Test / Idle
The TAP controller stays in this state as long as TMS is Low. Used to perform tests.
Capture - DR
The Boundary Scan Data Register (BSR) is loaded with input pin data.
Shift - DR
Shifts the selected test data registers by one stage tword its serial output.
Update - DR
Data is latched into the parallel output of the BSR when selected.
Capture - IR
Used to load the instruction register with a fixed instruction.
Shift - IR
Shifts the instruction register by one stage.
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