參數(shù)資料
型號(hào)： LU3X34FTR
英文描述： Quad 3 V 10/100 Ethernet Transceiver TX/FX
中文描述： 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯
文件頁(yè)數(shù)： 8/52頁(yè)
文件大?。?/td> 678K
代理商： LU3X34FTR
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
8
Lucent Technologies Inc.
Pin Descriptions
(continued)
Table 2. Twisted-Pair Magnetic Interface
Table 3. Twisted-Pair Transceiver Control/Transmitter Control
Table 4. MII Interface (RMII Mode)
Pin No.
6, 11, 28, 33
7, 10, 29, 32
Pin Name
TX+_[0:3]
TX–_[0:3]
I/O
O
Pin Description
Transmit Driver Pairs
. These pins are used to
transmit 100Base-T MLT-3 signals across Category
5 UTP cable. 10Base-T Manchester signals across
Category 3, 4, or 5 UTP cable in twisted-pair opera-
tion or PECL data in fiber mode.
Receive Pair
. These pins receive 100Base-T MLT-3
data or 10Base-T Manchester data from the UTP
cable in twisted-pair mode or PECL data in fiber
mode.
3, 14, 25, 36
2, 15, 24, 37
RX–_[0:3]
RX+_[0:3]
I
Pin No.
5, 12, 27, 34
Pin Name
REF100_[0:3]
I/O
I
Pin Description
Reference Pin for 100 Mbits/s Twisted-Pair
Driver
. The value of the connected resistor is 301
.
Reference Pin for 10 Mbits/s Twisted-Pair Driver
.
The value for the connected resistor is 4.65 k
.
Transmit Driver Edge Rate Control
. When set to 1,
the rise time of the transmit data will be less than
3.5 ns.
Network Interface 3-State Control
. When high, the
transmit drivers for the four ports are 3-stated.
22
REF10
I
127
ER
I
41
TPTXTR
I
Pin No.
99, 73, 53
113
102
Pin Name*
TXEN_[1:3]
TXEN_0
RMII_RXER_0
I/O
I
I
I/O
Pin Description
Transmit Enable for Ports 1—3.
Transmit Enable for Port 0.
Receiver Error Output for Port 0.
Indicates an
illegal code-group has been received.
Transmit Data for Port 0.
Receive Data for Port 0.
CRS_DV Output for Port 0
. During reset, this is an
input pin; logic level of 0 at this pin enables RMII
mode. This pin has an internal 40 k
pull-down
resistor that sets the MII interface to RMII mode with-
out an external component. After reset, CRS_DV
output for port 0 is asserted only during receive
activity.
Transmit Data for Port 1.
Receive Data for Port 1.
CRS_DV Output for Port 1
. During reset, this is an
input pin for PHY_address[2] configuration. This pin
has an internal 40 k
pull-down resistor that sets the
PHY_AD[2] to a 0 without an external component.
After reset, CRS_DV output for port 1 and is
asserted only during receive activity.
112, 111
110, 109
101
RMII_TXD_0[0:1]
RMII_RXD_0[0:1]
CRS_DV_0/
SMII_EN
I
I/O
I/O
↓
98, 97
96, 95
94
RMII_TXD_1[0:1]
RMII_RXD_1[0:1]
CRS_DV_1/
PHYAD[2]
I/O
O
I/O
↓
相關(guān)PDF資料
PDF描述
LU3X34FTR-HS128-DB Quad 3 V 10/100 Ethernet Transceiver TX/FX
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LU3X34FTR-HS128-DB 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX
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