- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄369872 > LU3X34FTR Quad 3 V 10/100 Ethernet Transceiver TX/FX PDF資料下載
參數(shù)資料
| 型號(hào)： | LU3X34FTR |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯 |
| 文件頁(yè)數(shù)： | 40/52頁(yè) |
| 文件大?。?/td> | 678K |
| 代理商： | LU3X34FTR |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)當(dāng)前第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
40
Lucent Technologies Inc.
Table 26. PHY Address Register (Register 19h)
11
Enable FEFI
1—Enable FEFI
0—Disable FEFI
This bit enables/disables far-end fault indi-
cator function for 100Base-FX and
10Base-T operation. It is initialized to the
logic level of FOSEL pin (pin 124, 117, 52,
and 46) at powerup or reset. After reset,
this bit is writable if and only if the FOSEL
register (bit 14 of register 17h) is set.
Reserved.
1—Force good link in 100 Mbit mode
0—Normal operation
Reserved.
1—Passes halt symbols to the MII
0—Normal operation
1—Loads the scrambler seed
0—Normal operation
Setting this bit loads the user seed stored
in register 19h into the 100Base-X scram-
bler. The content of this bit returns to 0
after the loading process is completed and
no transmit is active.
1—Burst mode
0—Normal operation
Setting this bit expands the 722
μ
s scram-
bler time-out period to 2,000
μ
s.
Reserved.
R/W
Pin
10
9
Reserved
RO
R/W
0h
0h
Force Good Link 100
8:6
5
Reserved
Accept Halt
RO
R/W
1h
0h
4
Load Seed
R/W, SC
0h
3
Burst Mode
R/W
0h
2:0
Reserved
RO
0h
Bit(s)
15:11
10:5
Name
Reserved
User Seed
Description
R/W
RO
R/W
Default
0h
21h
Reserved.
User-modifiable seed data. When the
load seed bit (bit 4 of register 18h) is set,
bits 10 through 0 of this register are
loaded into the 100Base-X scrambler.
These 5 bits store the part address used
by the serial management interface. Top
three of these bits are latched from the
pins during powerup of hard reset. Lower
2 bits are assigned automatically.
4:0
PHY Address
R/W
Pin
Bit(s)
Name
Description
R/W
Default
MII Registers
(continued)
Table 25. Config 100 Register (Register 18h)
(continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X34FTR-HS128-DB | Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR | Quad 3 V 10/100 Ethernet Transceiver(四通道10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器) |
| LU3X54FT | QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTL-HS208-DB | QUAD-FET for 10Base-T/100Base-TX/FX |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
| LU3X54FTL-HS208-DB | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。