- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369872 > LU3X34FTR Quad 3 V 10/100 Ethernet Transceiver TX/FX PDF資料下載
參數(shù)資料
| 型號： | LU3X34FTR |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯 |
| 文件頁數(shù)： | 35/52頁 |
| 文件大?。?/td> | 678K |
| 代理商： | LU3X34FTR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
Lucent Technologies Inc.
35
Preliminary Data Sheet
July 2000
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
MII Registers
(continued)
Table 18. Advertisement (Register 4h)
Bit(s)
15
Name
Next Page
Description
R/W
RO
Default
0h
1—Capable of next page function
0—Not capable of next page function
This bit is defaults to 0, indicating that
LU3X34FTR is not next page capable.
Reserved.
1—Remote fault has been detected
0—No remote fault has been detected
This bit is written by serial management
interface for the purpose of communicat-
ing the remote fault condition to the auto-
negotiation link partner.
These bits default to 0.
1—MAC sublayer is capable of pause-
based flow control
0—MAC sublayer not capable of pause-
based flow control
This bit advertises the MAC sublayer has
pause/flow control capability of operation
when set in full-duplex mode. This must
be set only when the PHY is advertising
10FD/100FD modes. At hardware reset,
this bit is set to 1, if the PAUSE pin
detects logic 1.
Note:
It is the user’s responsibility to
ensure that the flow control bit is set only
when the PHY is advertising
10FD/100FD modes.
This bit defaults to 0, indicating that the
LU3X34FTR does not support
100Base-T4.
This 4-bit field contains the advertised
ability of this PHY. At powerup or reset,
the logic level of 100FDEN, 100HDEN,
10FDEN, and 10HDEN pins are latched
into bits 8 through 5, respectively.
These 5 bits are hardwired to 00001h,
indicating that the LU3X34FTR supports
IEEE802.3 CSMA/CD.
14
13
Reserved
Remote Fault
RO
R/W
0h
0h
12:11
10
IEEEReserved
Flow Control
R/W
R/W
0h
Pin
9
Technology Ability Field for
100Base-T4
RO
0h
8:5
Technology Ability Field
R/W
Pin
4:0
Selector Field
RO
01h
相關PDF資料 |
PDF描述 |
|---|---|
| LU3X34FTR-HS128-DB | Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR | Quad 3 V 10/100 Ethernet Transceiver(四通道10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器) |
| LU3X54FT | QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTL-HS208-DB | QUAD-FET for 10Base-T/100Base-TX/FX |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
| LU3X54FTL-HS208-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
發(fā)布緊急采購，3分鐘左右您將得到回復。