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參數(shù)資料
| 型號(hào)： | LU3X34FTR |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯 |
| 文件頁數(shù)： | 16/52頁 |
| 文件大?。?/td> | 678K |
| 代理商： | LU3X34FTR |
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16
Lucent Technologies Inc.
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
Functional Description
(continued)
Receive Path
Receive data and control information are signaled in
10-bit segments. These 10-bit boundaries are delimited
by the SYNC signal. The connected MAC should gen-
erate these SYNC pulses every ten clocks. In
100 Mbits/s mode, each segment represents a new
byte of data. In 10 Mbits/s mode, each segment is
repeated ten times, so every ten segments represents
a new byte of data.
The receive sequence contains all of the information
found on the standard MII receive path. RXD[7:0] con-
vey packet data whenever the RXDV bit is set. During
an interframe gap, RXDV bit is set to 0 and RXD[7:0]
indicate receiver status. Bit RXD5 indicates the validity
of the upper nibble of the last byte of data of the previ-
ous frame. Bit RXD0 indicates an error detected by the
PHY in the previous frame. Both of these bits will be
valid in the segment immediately following a frame, and
will remain valid until the first data segment of the next
frame.
Transmit Data Path
Transmit data and control information are signaled in
10-bit segments similar to the receive path. These
10-bit boundaries are delimited by the SYNC signal.
The connected MAC should generate these SYNC
pulses every ten clocks. In 100 Mbits/s mode, each
new segment represents a new byte of data. In
10 Mbits/s mode, each segment is repeated ten times;
therefore, every ten segments represents a new byte of
data. The PHY can sample one of every ten segments.
The PHY is concerned only with packet data, so there
is no status information passed from the MAC to the
PHY during the interframe gap; this is unlike the
receive side.
Collision Detection
The PHY does not directly indicate that a collision has
occurred. It is left up to the MAC to detect the assertion
of both CRS and TXEN.
Table 10. Receive Data/Status Encoding
5-7508(F).r1
Figure 8. Transmit Sequence Diagram
CRS RXDV
X
RXD0
Rcvr
error in
the pre-
vious
frame.
RXD1
Speed:
0 =
10 Mbits/s
1 =
100 Mbits/s
RXD2
Duplex:
0 = half
1 = full
RXD3
Link:
0 = no link
1 = good link
RXD4
Jabber:
0 = OK
1 = detected
RXD5
RXD6
RXD7
1
0
Upper nibble:
0 = invalid
1 = valid
False carrier:
0 = OK
1 = detected
X
1
One Data Byte (two MII nibbles)
TXER
TXEN
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
1
2
3
4
5
6
7
8
9
10
11
SMII_CLK
SYNC
TXD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X34FTR-HS128-DB | Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR | Quad 3 V 10/100 Ethernet Transceiver(四通道10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器) |
| LU3X54FT | QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTL-HS208-DB | QUAD-FET for 10Base-T/100Base-TX/FX |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
| LU3X54FTL-HS208-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
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