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參數(shù)資料
| 型號(hào)： | LU3X34FTR |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯 |
| 文件頁數(shù)： | 26/52頁 |
| 文件大?。?/td> | 678K |
| 代理商： | LU3X34FTR |
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26
Lucent Technologies Inc.
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
Functional Description
(continued)
Operation Modes
The LU3X34FTR 10Base-T module is capable of oper-
ating in either half-duplex mode or full-duplex mode. In
half-duplex mode, the LU3X34FTR functions as an
IEEE802.3 compliant transceiver with fully integrated
filtering. The COL signal is asserted during collisions or
jabber events, and the CRS signal is asserted during
transmit and receive. In full-duplex mode, the
LU3X34FTR can simultaneously transmit and receive
data.
Manchester Encoder/Decoder.
Data encoding and
transmission begins when the transmit enable input
(TXEN) goes high and continues as long as the trans-
ceiver is in good link state. Transmission ends when the
transmit enable input goes low. The last transition
occurs at the center of the bit cell if the last bit is a 1, or
at the boundary of the bit cell if the last bit is 0.
Decoding is accomplished by a differential input
receiver circuit and a phase-locked loop that separates
the Manchester-encoded data stream into clock signals
and NRZ data. The decoder detects the end of a frame
when no more midbit transitions are detected. Within
one and a half bit times after the last bit, carrier sense
is deasserted.
Transmit Driver and Receiver.
The LU3X34FTR inte-
grates all the required signal conditioning functions in
its 10Base-T block such that external filters are not
required. Only an isolation transformer and impedance-
matching resistors are needed for the 10Base-T trans-
mit and receive interface. The internal transmit filtering
ensures that all the harmonics in the transmit signal are
attenuated properly.
Smart Squelch.
The smart squelch circuit is responsi-
ble for determining when valid data is present on the
differential receive. The LU3X34FTR implements an
intelligent receive squelch on the TPRX+/– differential
inputs to ensure that impulse noise on the receive
inputs will not be mistaken for a valid signal. The
squelch circuitry employs a combination of amplitude
and timing measurements (as specified in the IEEE
802.3 10Base-T standard) to determine the validity of
data on the twisted-pair inputs.
The signal at the start of the packet is checked by the
analog squelch circuit and any pulses not exceeding
the squelch level (either positive or negative, depend-
ing upon polarity) will be rejected. Once this first
squelch level is overcome correctly, the opposite
squelch level must then be exceeded within 150 ns.
Finally, the signal must exceed the original squelch
level within an additional 150 ns to ensure that the input
waveform will not be rejected.
Only after all of these conditions have been satisfied
will a control signal be generated to indicate to the
remainder of the circuitry that valid data is present.
Valid data is considered to be present until the squelch
level has not been generated for a time longer than
200 ns, indicating end of packet. Once good data has
been detected, the squelch levels are reduced to mini-
mize the effect of noise, causing premature end-of-
packet detection. The receive squelch threshold level
can be lowered for use in longer cable applications.
This is achieved by setting bit 11 of register address
1Ah.
Carrier Sense.
Carrier sense (CRS) is asserted due to
receive activity once valid data is detected via the
smart squelch function.
For 10 Mbits/s half-duplex operation, CRS is asserted
during either packet transmission or reception.
For 10 Mbits/s full-duplex operation, the CRS is
asserted only due to receive activity.
In repeater mode, CRS is only asserted due to receive
activity. CRS is deasserted following an end of packet.
Collision Detection.
The RMII does not have a colli-
sion pin. Collision is detected internal to the MAC,
which is generated by an AND function of TXEN and
CRS derived from CRS_DV. CRS_DV cannot be
directly ANDed with TXEN because CRS_DV may tog-
gle at the end of a frame to provide separation between
CRS and RXDV. The internal MII will still generate the
COL signal, but this information is not passed to the
MAC via the RMII.
Jabber Function.
The jabber function monitors the
LU3X34FTR's output and disables the transmitter if it
attempts to transmit a longer than legal-sized packet. If
TXEN is high for greater than 24 ms, the 10Base-T
transmitter will be disabled. Once disabled by the jab-
ber function, the transmitter stays disabled for the
entire time that the TXEN signal is asserted. This sig-
nal has to be deasserted for approximately 256 ms (the
unjab time) before the jabber function re-enables the
transmit outputs. The jabber function can be disabled
by setting bit 10 of register 1Ah.
Link Test Function.
A link pulse is used to check the
integrity of the connection with the remote end. If valid
link pulses are not received, the link detector disables
the 10Base-T twisted-pair transmitter, receiver, and col-
lision detection functions.
The link pulse generator produces pulses as defined in
the IEEE802.3 10Base-T standard. Each link pulse is
nominally 100 ns in duration and is transmitted every
16 ms, in the absence of transmit data.
相關(guān)PDF資料 |
PDF描述 |
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| LU3X34FTR-HS128-DB | Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR | Quad 3 V 10/100 Ethernet Transceiver(四通道10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器) |
| LU3X54FT | QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTL-HS208-DB | QUAD-FET for 10Base-T/100Base-TX/FX |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
| LU3X54FTL-HS208-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
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