參數(shù)資料
型號: LU3X34FTR
英文描述: Quad 3 V 10/100 Ethernet Transceiver TX/FX
中文描述: 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯
文件頁數(shù): 34/52頁
文件大小: 678K
代理商: LU3X34FTR
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
34
Lucent Technologies Inc.
Table 16. PHY Identifier (Register 2h)
Table 17. PHY Identifier (Register 3h)
3
Autonegotiation Ability
1—Capable of autonegotiation
0—Not capable of autonegotiation
This bit defaults to 1, indicating that
LU3X34FTR is capable of autonegotia-
tion.
1—Link is up
0—Link is down
This bit reflects the current state of the
link-test-fail state machine. Loss of a valid
link causes a 0 latched into this bit. It
remains 0 until this register is read by the
serial management interface.
1—Jabber condition detected
0—Jabber condition not detected
During 10Base-T operation, this bit indi-
cates the occurrence of a jabber condi-
tion. It is implemented with a latching
function so that it becomes set until it is
cleared by a read.
1—Extended register set
0—No extended register set
This bit defaults to 1, indicating that the
LU3X34FTR implements extended regis-
ters.
RO
1h
2
Link Status
RO,
LL
0h
1
Jabber Detect
RO,
LH
0h
0
Extended Capability
RO
1h
Bit(s)
15:0
Name
Description
IEEE address
R/W
RO
Default
0043h
PHY-ID[15:0]
Bit(s)
15:0
Name
Description
IEEE
address/Model
No./ Rev. No.
R/W
RO
Default
7440h
PHY-ID[15:0]
Bit(s)
Name
Description
R/W
Default
MII Registers
(continued)
Table 15. Status Register Bit Definitions (Register 1h)
(continued)
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