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參數(shù)資料
| 型號： | LU3X34FTR |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯 |
| 文件頁數(shù)： | 38/52頁 |
| 文件大?。?/td> | 678K |
| 代理商： | LU3X34FTR |
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LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
38
Lucent Technologies Inc.
MII Registers
(continued)
Table 22. False Carrier Counter (Register 13h)
Table 23. Receive Error Counter (Register 15h)
Table 24. PHY Control/Status Register (Register 17h)
Bit(s)
15:0
Name
Description
R/W
RO,
COR
Default
0h
False Carrier Count
Number of false carrier conditions since
reset or read. The counter is incriminated
once for each packet that has false carrier
condition detected. This counter may roll
over depending on value of CSMODE bit
(bit 13 of register 17h).
Bit(s)
15:0
Name
Description
R/W
RO,
COR
Default
0h
RX Error Count
Number of receive errors since last reset.
The counter is incriminated once for each
packet that has receive error condition
detected. This counter may roll over
depending on value of the CSMODE bit
(bit 13 of register 17h).
Bit(s)
15
14
Name
Reserved
FOSEL
Description
R/W
RO
RO
Default
0h
Pin
Reserved.
1—Fiber mode
0—TX mode
For 100Base-X operation, this bit deter-
mines whether LU3X34FTR interfaces
with the network through the internal
100Base-TX transceiver or using external
fiber-optic transceiver. It is initialized to the
logic level of FOSEL pin (pin 124, 117, 46,
and 52 for four PHYs) at powerup or reset.
1—Counter sticks at FFFFh
0—Counters roll over
This bit controls the operation of isolate
counter, false carrier counter, and receive
error counters.
1—3-state transmit pairs
0—Normal operation
When this bit is set, the twisted-pair trans-
mitter outputs if all four ports are 3-stated.
Note that the twisted-pair transmit driver
can be 3-stated by either this bit or the
TPTXTR pin (pin 41).
13
CSMODE
R/W
0h
12
TPTXTR
R/W
Pin
11
ThunderLAN Interrupt Enable 1—MDIO ThunderLAN interrupt enabled
0—MDIO ThunderLAN interrupt disabled
This bit enables/disables the TI Thunder-
LAN interrupt mechanism.
R/W
0h
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X34FTR-HS128-DB | Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR | Quad 3 V 10/100 Ethernet Transceiver(四通道10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器) |
| LU3X54FT | QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTL-HS208-DB | QUAD-FET for 10Base-T/100Base-TX/FX |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
| LU3X54FTL-HS208-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
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