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參數(shù)資料
| 型號(hào)： | LU3X34FTR |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯 |
| 文件頁(yè)數(shù)： | 31/52頁(yè) |
| 文件大?。?/td> | 678K |
| 代理商： | LU3X34FTR |
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Lucent Technologies Inc.
31
Preliminary Data Sheet
July 2000
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
14
Loopback
1—Enable loopback mode
0—Disable loopback mode
This bit controls the PHY loopback opera-
tion that isolates the network transmitter
outputs (TPTX+/– and FOTX+/–) and
routes the MII transmit data to the MII
receive data path. This function should
only be used when autonegotiation is dis-
abled (bit 12 = 0). The specific PHY
(10Base-T or 100Base-X) used for this
operation is determined by bits 12 and 13
of this register.
1—100 Mbits/s
0—10 Mbits/s
Link speed is selected by this bit or by
autonegotiation if bit 12 of this register is
set (in which case, the value of this bit is
ignored). At powerup or reset, this bit will
be set unless ANEN, FD100, and HD100
pins are all in logic low state.
1—Enable autonegotiation process
0—Disable autonegotiation process
This bit determines whether the link speed
should be set up by the autonegotiation
process. It is set at powerup or reset if the
ANEN pin detects a logic 1 input level.
1—Powerdown
0—Normal operation
Setting this bit puts the LU3X34FTR into
powerdown mode. During the powerdown
mode, TPTX+/– and all LED outputs are
3-stated, FOTX+/– outputs are turned off,
and the MII interface is isolated. RESETZ
is used to clear register.
Note:
Powerdown is an optional function
and is not implemented in this device. Set-
ting this bit does not significantly impact
the power consumption.
1—Isolate PHY from MII
0—Normal operation
Setting this control bit isolates the part
from the MII, with the exception of the
serial management interface. When this
bit is asserted, the LU3X34FTR does not
respond to TXD[3:0], TXEN, and TXER
inputs, and it presents a high impedance
on its TXCLK, RXCLK, RXDV, RXER,
RXD[3:0], COL, and CRS outputs.
R/W
0h
13
Speed Selection
R/W
Pin
12
Autonegotiation Enable
R/W
Pin
11
Powerdown
R/W
0h
10
Isolate
R/W
Pin
Bit(s)
Name
Description
R/W
Default
MII Registers
(continued)
Table 14. Control Register (Register 0h)
(continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X34FTR-HS128-DB | Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR | Quad 3 V 10/100 Ethernet Transceiver(四通道10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器) |
| LU3X54FT | QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTL-HS208-DB | QUAD-FET for 10Base-T/100Base-TX/FX |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
| LU3X54FTL-HS208-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
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