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參數(shù)資料
| 型號(hào)： | LPC47B37X |
| 廠商： | SMSC Corporation |
| 英文描述： | 100 Pin Enhanced Super I/O for LPC Bus with SMBus Controller for Commercial Applications |
| 中文描述： | 100引腳增強(qiáng)的超級(jí)I / O控制器，帶有SMBus為商業(yè)應(yīng)用的LPC總線 |
| 文件頁(yè)數(shù)： | 142/254頁(yè) |
| 文件大?。?/td> | 659K |
| 代理商： | LPC47B37X |
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An example logic equation for the nSMI output for SMI registers 1 and 2 is as follows:
nSMI = (EN_PINT and IRQ_PINT) or (EN_U2INT and IRQ_U2INT) or (EN_U1INT and IRQ_U1INT) or
(EN_FINT and IRQ_FINT) or (EN_WDT and IRQ_WDT) or (EN_MINT and IRQ_MINT) or (EN_KINT
and IRQ_KINT) or (EN_SMBus and IRQ_SMBus) or (EN_RI1 and IRQ_RI1) or (EN_P12 and IRQ_P12)
or (EN_RI2 and IRQ_RI2)
Note: The prefixes EN and IRQ are used above to indicate SMI enable bit and SMI status bit
respectively.
SMI Registers
The SMI event bits for the GPIOs and the Fan tachometer events are located in the SMI status and
Enable registers 3-5. The polarity of the edge used to set the status bit and generate an SMI is
controlled by the polarity bit of the control registers. For non-inverted polarity (default) the status bit is
set on the low-to-high edge. If the EETI function is selected for a GPIO then both a high-to-low and a
low-to-high edge will set the corresponding SMI status bit. Status bits for the GPIOs are cleared on a
write of ‘1’.
The SMI logic for the P16 event is implemented such that the output of the status bit for the event is
combined with the corresponding enable bit in order to generate an SMI.
The P12 and P16 bits enable an SMI event on single high-to-low edge or on both high-to-low and low-
to-high edges. Default is single edge. There is also a polarity select bit for P12 in the Configuration
Register 0xF0 in Logical Device 7. The register that selects the edge, Edge Select register, is located
at the address programmed in the Base I/O Address register in the Logical Device A at an offset of 21h.
Refer also to PME Status and Enable register 2. See the Runtime Registers sections for description on
these registers.
If both edges are selected for generating an SMI via P16, then the SMI is asserted on each edge until
the P16 SMI status bit is cleared. If both edges are selected for generating an SMI via P12, then a
short pulse (20ns) is generated on each edge. However the P12 SMI status bit is set on each edge
until cleared. The P12 SMI is not recommended to be used in this mode of operation.
Note that P12 and P16 SMI status bits are cleared on by write of ‘1’. The SMI generated by P16 is also
deasserted when the P16 SMI status bit is written to ‘1’. However, the SMI generated by P12 is cleared
at the source.
The SMI logic for the P16 event is implemented such that the output of the status bit for the event is
combined with the corresponding enable bit in order to generate an SMI.
The SMI registers are accessed at an offset from Runtime Registers Block (see Runtime register
section for more information).
The SMI event bits for the super I/O devices are located in the SMI status and enable register 1 and 2.
All of these status bits are cleared at the source except for IRINT, which is cleared by a read of the
SMI_STS2 register; these status bits are not cleared by a write of ‘1’. The SMI logic for these events is
implemented such that each event is directly combined with the corresponding enable bit in order to
generate an SMI.
See the “Runtime Registers” section for the definition of these registers.
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