參數(shù)資料
型號: LPC47B37X
廠商: SMSC Corporation
英文描述: 100 Pin Enhanced Super I/O for LPC Bus with SMBus Controller for Commercial Applications
中文描述: 100引腳增強(qiáng)的超級I / O控制器,帶有SMBus為商業(yè)應(yīng)用的LPC總線
文件頁數(shù): 13/254頁
文件大小: 659K
代理商: LPC47B37X
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13
Indication of 32kHz Clock
There is a bit to indicate whether or not the
32kHz clock input is connected to the
LPC47B37x. This bit is located at bit 0 of the
CLOCKI32 register at 0xF0 in Logical Device A.
This register is powered by VTR and reset on a
VTR POR.
Bit[0] (CLK32_PRSN) is defined as follows:
0=32kHz clock is connected to the CLKI32 pin
(default).
1=32kHz clock is not connected to the CLKI32
pin (pin is grounded).
Bit 0 controls the source of the 32kHz (nominal)
clock for the fan tachometer logic, the LED blink
logic, the WDT and the “wake on specific key”
logic. When the external 32kHz clock is
connected, that will be the source for the fan
tachometer, LED, WDT and “wake on specific
key” logic. When the external 32kHz clock is not
connected, an internal 32kHz clock source will
be derived from the 14MHz clock for the fan
tachometer, LED, WDT and “wake on specific
key” logic.
The following functions will not work under VTR
power (VCC removed) if the external 32kHz
clock is not connected. These functions will work
under VCC power even if the external 32kHz
clock is not connected.
Fan tachometer
Wake on specific key
LED blink
WDT
Trickle Power Functionality
When the LPC47B37x is running under VTR
only, the PME wakeup events are active and (if
enabled) able to assert the nIO_PME pin active
low. The following lists the wakeup events:
UART 1 Ring Indicator
UART 2 Ring Indicator
Keyboard data
Mouse data
Wake on Specific Key Logic
Fan Tachometer (Note)
GPIOs for wakeup. See below.
Note:
PME when VCC=0. Clear the enable bits for the
fan tachometer before removing fan power.
The Fan Tachometer can generate a
The following requirements apply to all I/O pins
that are specified to be 5 volt tolerant.
I/O
buffers
that
compatible are powered by VCC. Under
VTR power (VCC=0), these pins may only
be configured as inputs. These pins have
input buffers into the wakeup logic that are
powered by VTR.
I/O buffers that may be configured as either
push-pull or open drain under VTR power
(VCC=0), are powered by VTR. This means
they will, at a minimum, source their
specified current from VTR even when VCC
is present.
are
wake-up
event
The GPIOs that are used for PME wakeup inputs
are GP10-GP17, GP20-GP27, GP30-GP37,
GP41, GP43, GP50-GP57, GP60, GP61. These
GPIOs function as follows (with the exception of
GP53, GP60 and GP61 - see below):
Buffers are powered by VCC, but in the
absence of VCC they are backdrive
protected (they do not impose a load on any
external VTR powered circuitry). They are
wakeup compatible as inputs under VTR
power. These pins have input buffers into
the wakeup logic that are powered by VTR.
All GPIOs listed above are for PME wakeup as a
GPIO function (or alternate function). Note that
GP33 cannot be used for wakeup under VTR
power (VCC=0) since this is the fan control pin
which comes up as output and low following a
VCC POR and Hard Reset. GP53 cannot be
used for wakeup under VTR power since this has
the IRTX function and comes up as output and
low following a VTR POR, a VCC POR and Hard
Reset. Also, GP33 reverts to its non-inverting
GPIO output function when VCC is removed
from the part. GP43 reverts to the basic GPIO
function when VCC is removed form the part, but
its programmed input/output, invert/non-invert
output buffer type is retained.
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