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參數(shù)資料
| 型號： | LH540235 |
| 廠商： | Sharp Corporation |
| 英文描述： | 2048 x 18 / 4096 x 18 Synchronous FIFOs |
| 中文描述： | 2048 ×四千零九十六分之十八× 18同步FIFO的 |
| 文件頁數(shù)： | 7/46頁 |
| 文件大?。?/td> | 369K |
| 代理商： | LH540235 |
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PIN DESCRIPTIONS (cont’d)
PIN
NAME
PIN
TYPE
1
DESCRIPTION
LD
Load
I
When LD is LOW, the data word on D
0
– D
17
(the data inputs) is written into a
programmable-flag-offset register,
or into the Control Register (when in the
Enhanced Operating Mode),
on the LOW-to-HIGH transition of WCLK, whenever
WEN is LOW (see Table 3). Also, when LD is LOW, a word is read to Q
0
– Q
17
(the
data outputs) from the offset registers
and/or the Control Register (when in the
Enhanced Operating Mode)
on the LOW-to-HIGH transition of RCLK, whenever
REN is LOW (see again Table 3, and particularly the Notes following this table).
When LD is HIGH, normal FIFO write and read operations are enabled.
Tie LOW in Standard Mode, cascading is not supported.
In the Enhanded
Operating Mode, whenever Control Register Bit06 is HIGH, WXI/WEN
2
functions as a second write-enable signal, WEN
2
, which is ANDed with WEN
to produce an effective internal write-enable signal.
Tie LOW in Standard Mode.
In the Enhanced Operating Mode, whenever
Control Register Bit06 is HIGH, RXI/REN
2
functions as a second read-enable
signal, REN
2
,which is ANDed with REN to produce an effective internal read-
enable signal.
When FF is LOW, the FIFO is full; further advancement of its internal write-address
pointer, and further data writes through its Data Inputs into its internal memory
array, are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to
WCLK.
When PAF is LOW, the FIFO is ‘a(chǎn)lmost full,’ based on the almost-full-offset value
programmed into the FIFO’s Almost-Full Offset Register. The default value of this
offset at reset is 127
10
, measured from ‘full’ (see Table 4). In the IDT-Compatible
Operating Mode, PAF is asynchronous.
In the Enhanced Operating Mode, PAF is
synchronized to WCLK after a reset operation, according to the state of
Control Register bit 04 (see Table 5).
In the standalone or paralleled configuration, whenever
HF is LOW the device is
more than half full. In IDT-Compatible Operating Mode, HF is asynchronous;
in the
Enhanced Operating Mode, HF may be synchronized either to WCLK or to
RCLK after a reset operation, according to the state of Control Register bits
02 and 03 (see Table 5).
When PAE is LOW, the FIFO is ‘a(chǎn)lmost empty,’ based on the almost-empty-offset
value programmed into the FIFO’s Almost-Empty Offset Register. The default value
of this offset at reset is 127
10
, measured from ‘empty’ (see Table 4). In IDT-
Compatible Operating Mode, PAE is asynchronous.
In the Enhanced Operating
Mode, PAE is synchronized to RCLK after a reset operation, according to the
state of Control Register bit 01. (See Table 5.)
When EF is LOW, the FIFO is empty; further advancement of its internal read-
address pointer, and further readout of data words from its internal memory array to
its Data Outputs, are inhibited. When EF is HIGH, the FIFO is not empty. EF is
synchronized to RCLK.
In the Enhanced Operating Mode, Control Register bit 06 is HIGH, EF
2
behaves as an exact duplicate of EF, but delayed by one full cycle of RCLK
with respect to EF.
Data outputs to drive an 18-bit bus.
+3.3 V power-supply pins.
0 V ground pins.
WEN
2
Write Enable 2
I
REN
2
Read Enable 2
I
FF
Full Flag
O
PAF
Programmable
Almost-Full Flag
O
HF
Half-Full Flag
O
PAE
Programmable
Almost-Empty
Flag
O
EF
Empty Flag
O
EF
2
Empty Flag 2
O
Q
0
– Q
17
V
CC
V
SS
Data Outputs
Power
Ground
O/Z
V
V
NOTES:
1
I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level
2
The ostensible differences in signal assertiveness are reconciled before ANDing.
BOLD ITALIC = Enhanced Operating Mode
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
7
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