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參數(shù)資料
| 型號： | LH540235 |
| 廠商： | Sharp Corporation |
| 英文描述： | 2048 x 18 / 4096 x 18 Synchronous FIFOs |
| 中文描述： | 2048 ×四千零九十六分之十八× 18同步FIFO的 |
| 文件頁數(shù)： | 23/46頁 |
| 文件大?。?/td> | 369K |
| 代理商： | LH540235 |
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t
DS
t
ENS
Q
0
- Q
17
REN
RCLK
EF
OE
WEN
540235-8
VD0 (FIRST
D
1
D
2
D
3
D
4
D
0
D
1
t
FRL (2)
t
SKEW2 (1)
t
REF
t
A (3)
t
A
t
OLZ
t
OE
D
0
- D
17
WCLK
NOTES:
1. t
is the minimum time between a rising RCLK edge and a rising
WCLK edge for FF to change predictably during the current clock cycle.
If the time between the rising edge of RCLK and the rising edge of
WCLK is less than t
, then it is not guaranteed that FF will change
state until the next following WCLK edge.
2. t
(First-Read Latency) is the minimum time between a rising WCLK
edge and a rising RCLK edge to assure a correct readout of the first data
word D
in response to the next RCLK edge. Thus, t
= t
CLK
+ t
.
If t
FRL
is not met, D
0
may be available either at t
CLK
+ t
SKEW2
, or after
one more clock cycle delay at 2 t
+ t
. The First-Read Latency
timing restrictions apply only when the FIFO has been empty (EF = LOW).
3. EF may be used to determine when the first data word D
may be read.
D
0
always is available on the next cycle after EF has gone HIGH.
Figure 9. Latency for the First Data Word After a
Reset Operation, With Simultaneous Read and Write
TIMING DIAGRAMS (cont’d)
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
23
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| LH5420 | 256 x 36 x 2 Bidirectional FIFO |
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| LH5424-QT | 5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs-LED |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH540235M-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| LH540235M-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| LH540235M-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| LH540235U-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| LH540235U-25 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:2048 x 18 / 4096 x 18 Synchronous FIFOs |
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