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參數(shù)資料
| 型號： | LH540235 |
| 廠商： | Sharp Corporation |
| 英文描述： | 2048 x 18 / 4096 x 18 Synchronous FIFOs |
| 中文描述： | 2048 ×四千零九十六分之十八× 18同步FIFO的 |
| 文件頁數(shù)： | 20/46頁 |
| 文件大?。?/td> | 369K |
| 代理商： | LH540235 |
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PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
PAE goes LOW whenever the FIFO is ‘a(chǎn)lmost empty’;
that is, whenever subtracting the value of the FIFO’s
internal write pointer from the value of its internal read
pointer yields a difference which is less than q + 1, where
‘q’ is the value of the Programmable-Almost-Empty-Flag
Offset. The subtraction is performed using modular arith-
metic, modulo the total nominal number of 18-bit words
in the FIFO’s physical memory, which is 2048 for the
LH540235 or 4096 for the LH540245 respectively.
The default value of q after the completion of a reset
operation is 127
10
. However, q may be set to any value
which does not exceed this total nominal number of words
for the device, as explained in the description of Load
(LD).
If the FIFO has been reset by asserting RS (LOW), and
no write operations have been performed since the com-
pletion of the reset operation, then PAE is LOW (see Table
4).
If q is still at its default value, PAE is LOW whenever
the FIFO is from one-eighth full to completely empty.
In the IDT-Compatible Operating Mode, PAE changes
from HIGH to LOW only after a LOW-to-HIGH transition
of the Read Clock RCLK, and from LOW to HIGH only
after a LOW-to-HIGH transition of the Write Clock WCLK.
Thus, in this operating mode, PAE behaves as an ‘a(chǎn)syn-
chronous flag.’
In the Enhanced Operating Mode, on the other
hand, PAE gets updated only after a LOW-to-HIGH
transition of the Read Clock RCLK, and thus behaves
as a ‘synchronous flag,’ whenever Control Register
bit 01 is HIGH (see Table 5).
EMPTY FLAG (EF)
EF goes LOW whenever the FIFO is completely empty.
That is, whenever the FIFO’s internal read pointer has
completely caught up with its internal write pointer; so
that, if another word were to be read out, it would have to
come from the physical memory location which is now in
position to be written into by the next requested write
operation. Read operations are inhibited whenever EF is
LOW, regardless of the assertion or deassertion of Read
Enable (REN).
If the FIFO has been reset by asserting RS (LOW), and
no write operations have been performed since the
completion of the reset operation, then EF is LOW. (See
Table 4.)
EF gets updated after a LOW-to-HIGH transition of the
Read Clock RCLK.
READ EXPANSION OUT/EMPTY FLAG 2(RXO/EF
2
)
RXO/
EF
2
is a dual-purpose signal. In ‘standalone’
operation, it has no function. In IDT-compatible ‘cas-
caded’ operation, it behaves as a Read Expansion Output
BOLD ITALIC = Enhanced Operating Mode
(RXO) signal to coordinate writing operations with the
next FIFO in the cascade. Under these same conditions,
also, the dual purpose RXI/
REN
2
and WXI/
WEN
2
inputs
behave as Read Expansion Input (RXI) and Write Expan-
sion Input (WXI) signals respectively.
When two or more LH540235 or LH540245 FIFOs are
operating in IDT-compatible ‘cascaded’ mode as a deeper
‘effective FIFO,’ the dual-purpose RXI/
REN
2
and
WXI/
WEN
2
inputs behave as Read Expansion Input (RXI)
and Write Expansion Input (WXI) signals respectively. An
IDT-style cascade of these FIFO devices has a ‘daisy-
chain’ ring configuration; the Read Expansion Input (RXI)
of each FIFO is connected to RXO (RXO/
EF
2
, behaving
as RXO) of the previous FIFO in the ring, with RXI of the
‘first-load’ or ‘master’ FIFO being connected to RXO of
the last FIFO so as to complete the ring. Similar connec-
tions are made for each FIFO in the ring, parallel to these
RXO-to-RXI connections, for Write Expansion Input
(WXI) and Write Expansion Output (WXO).
When the last physical location has been read in a
FIFO operating in IDT-style cascaded mode, a LOW-go-
ing pulse is emitted by that FIFO on its RXO output;
otherwise, RXO remains constantly HIGH. This LOW-go-
ing RXO pulse serves as a ‘read token’ in the token-pass-
ing FIFO-cascading scheme; it is passed on to the next
FIFO in the ring via its RXI input. When this next FIFO
receives the read token, it is activated for reading at the
next valid RCLK.
After a FIFO emits an RXO pulse, the FIFO is deacti-
vated for reading at the next valid RCLK. Also, its data
outputs go into high-Z state, regardless of the assertion
or deassertion of its Output Enable (OE) control input,
until it again receives the token. Simultaneously, the next
FIFO in the ring is activated for reading.
The foregoing description applies both to the ‘first-load’
or ‘master’ FIFO in the ring, and to any and all ‘slave’
FIFOs in the ring. However, RXO has no necessary
function for a FIFO which is operating in ‘standalone’
mode. Consequently, in that mode, RXO is never as-
serted, and remains constantly HIGH. A FIFO is initialized
into ‘standalone’ mode, into ‘cascaded master’ mode, or
into ‘cascaded slave’ mode according to the state of its
WXI/
WEN
2
, RXI/
REN
2
, and FL/
RT
control inputs during
a reset operation.
It also may be forced into inter-
locked-paralleled mode by EMODE (see Table 1, Ta-
ble 2, and Table 5).
In the Enhanced Operating Mode, RXO/EF
2
be-
haves as a second Empty Flag EF
2
. EF
2
is an exact
duplicate of the main Empty Flag EF except that it is
delayed with respect to EF By one full cycle of the
Read Clock RCLK.
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
20
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| LH540235M-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
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| LH540235U-25 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:2048 x 18 / 4096 x 18 Synchronous FIFOs |
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