參數(shù)資料
型號(hào)： LH540235
廠商： Sharp Corporation
英文描述： 2048 x 18 / 4096 x 18 Synchronous FIFOs
中文描述： 2048 ×四千零九十六分之十八× 18同步FIFO的
文件頁(yè)數(shù)： 34/46頁(yè)
文件大小： 369K
代理商： LH540235
Q [17:0]
RCLK
FL/RT
FF
PAF
HF
PAE
EF
REN
1
540235-28
D
R1
t
ENS
t
RSF
D
RT12
D
RT2
NOTES:
1. It is not necessary for REN to be LOW for the device to recognize a retransmit request.
2. In order to actually read data words from the memory arrary, in IDT-Compatible
Operating Mode, REN = LOW;
in Enhanced Operating Mode, also REN
= HIGH
(and OE = LOW, if Control Register bit 05 = HIGH).
In any case, LD = HIGH.
3. D
is the data item in physical location zero of the FIFO memory array.
4. The asynchronous intermediate flags (corresponding to LOW Control-Register bits) will
show correct status three RCLK cycles after a retransmit operation, as is shown above.
(RT
, in the above RCLK waveform.)
5. The intermediate flags which have been synchronized to RCLK, by setting the appropriate
Control-Register bits to HIGH will show correct status after B
retransmit operation. (RT
, in the above RCLK waveform.)
6. The intermediate flags which have been synchronized to WCLK, by setting the appropriate
Control-Register bits HIGH, will show correct status on the second WCLK rising edge after A
assuming that t
SKEW1
was satisfied at A
WCLK rising edge after A
7. Immediately after a reset operation, before any write operations have taken place, a retransmit
operation is a 'no-op', and does not change the state of any FIFO registers or flags.
8. In the special case that the FIFO memory array contains
only one
valid data item, the status
of HF and PAF should be ignored on a retransmit.
t
ENS
t
ENH
D
R2
t
A
t
A
t
PAF
R
1
R
2
RT
1
RT
2
RT
3
RT
4
t
WFF
t
HF
t
PAE
t
REF
NEW VALID FF
NEW VALID PAF
NEW VALID HF
NEW VALID PAE
NEW VALID EF
UNKNOWN
UNKNOWN
UNKNOWN
PREVIOUS VALID FF
PREVIOUS VALID PAF
PREVIOUS VALID HF
PREVIOUS VALID PAE
PREVIOUS VALID EF
A
B
t
A
t
A
Figure 21. Retransmit Timing,
IDT-Compatible Operating Mode
TIMING DIAGRAMS (cont’d)
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
34
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