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參數(shù)資料
| 型號： | LH540235 |
| 廠商： | Sharp Corporation |
| 英文描述： | 2048 x 18 / 4096 x 18 Synchronous FIFOs |
| 中文描述： | 2048 ×四千零九十六分之十八× 18同步FIFO的 |
| 文件頁數(shù)： | 40/46頁 |
| 文件大小： | 369K |
| 代理商： | LH540235 |
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Depth Cascading Using Pipelining
Using the pipelining approach, depth cascading is
implemented by connecting the required number of
LH540235/45s in series. Within the cascade, the Data
Outputs of each device are connected to the Data Inputs
of the next device. (See Figure 30.) All devices in the
cascade must be in
the Enhanced Operating Mode
;
thus, their
EMODE
inputs must be grounded.
Successive devices in the cascade are crosscoupled;
they control each other, using a ‘handclasp’ scheme for
crossconnecting their control inputs and their status out-
puts. (See again Figure 30.) The input side of the first
device, and the output side of the last device, are not
crosscoupled to other devices. Their control/status and
clock pins are connected to the external system.
For the FIFO devices within the cascade, transferring
data from each device to the next device is governed by
a clock. Preferably, the same clock should be used at
every FIFO-to-FIFO data-transfer interface boundary
within the cascade. This ‘Transfer Clock’ may be either
the external Write Clock, or the external Read Clock. If
both of these two clocks are periodic and free-running,
the faster of the two is the obvious choice for the ‘Transfer
Clock.’ Of course, in principle, the ‘Transfer Clock’ may
even be some other, totally-different clock.
The Empty Flag of each device is used to govern
writing into the next device, and the Full Flag of each
device is used to govern reading from the preceding
device. Since the standard Empty Flag EF occurs one
RCLK cycle too early to properly enable/disable the next
device,
the duplicate Empty Flag EF
2
is used instead;
EF
2
is an exact copy of EF, except that it is delayed
by one full RCLK cycle with respect to EF.
Also, since the usual enable signals WEN and REN
have the wrong polarity to function properly in this ‘hand-
clasp’ mode, they are grounded for all devices within the
cascade.
The duplicate but inverted signals WEN
2
and REN
2
are used instead.
EF
2
, WEN
2
, and REN
2
are available only in En-
hanced Operating Mode. They share the same pins
which in IDT-Compatible Operating Mode are used
respectively for RXO, WXI, and RXI. Hence, for pipe-
lined operation, all devices in the cascade must be in
the Enhanced Operating Mode; their EMODE control
inputs must be grounded.
When all of the foregoing conditions have been met in
the interconnection of the pipelined array, then: At each
device-to-device interface boundary within the array, a
data word is transferred from the upstream device to the
downstream device after everytransfer-clock rising edge,
as long as the upstream device is not empty and the
downstream device is not full.
Width Expansion Along With Depth Cascading
In principle, width expansion may be used with either
of the two possible depth-cascading schemes.
However, when using the token-passing depth-cas-
cading scheme, width expansion reduces simply to plac-
ing two or more cascades in parallel. In this mode of
interconnection, no architectural support is available for
interlocked-paralleled operation. Composite-flag logic
may, of course, be designed to fit any complete array
configuration, to determine meaningful full and empty
indications for the entire array. This logic may, for in-
stance, OR the FF and EF signals from the devices at the
same relative position in each of the paralleled cascades,
and then AND all of the rank-FF signals together; and
likewise for all of the rank-EF
signals. Then, the entire
array is indicated to be full, if all ranks of devices
(across the paralleled cascades) are individually full;
and, similarly for empty.
When using the pipelined depth-cascading scheme,
on the other hand, the first rank of devices (the one which
receives input data words from the external system) and
the last rank of devices (the one which provides output
data words to the external system) may be operated in an
interlocked-paralleled manner. Figure 31 shows a sug-
gested interconnection scheme for two paralleled cas-
cades, each three devices deep. The entire array of
Figure 31 would comprise a 12288
×
36 ‘effective FIFO,’
if implemented with 4096
×
18 LH540245 devices. When-
ever the number of paralleled cascades exceeds two, a
small amount of external logic is necessary to implement
the interlocking.
BOLD ITALIC = Enhanced Operating Mode
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
40
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LH5420 | 256 x 36 x 2 Bidirectional FIFO |
| LH5424-S | 5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs-LED |
| LH5424-QT | 5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs-LED |
| LH5424-T | 5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs-LED |
| LH5424-SU | 5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs-LED |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH540235M-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| LH540235M-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| LH540235M-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| LH540235U-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| LH540235U-25 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:2048 x 18 / 4096 x 18 Synchronous FIFOs |
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