LH540235/45
2048
×
18 / 4096
×
18 Synchronous FIFOs
FEATURES
Fast Cycle Times: 20/25/35 ns
Pin-Compatible Drop-In Replacements for
IDT72235B/45B FIFOs
Choice of IDT-Compatible or
Enhanced
Operating
Mode; Selected by an Input Control Signal
Device Comes Up into One of Two Known Default
States at Reset Depending on the State of the
EMODE
Control Input: Programming is Allowed, but
is not Required
Internal Memory Array Architecture Based on CMOS
Dual-Port SRAM Technology, 2048
×
18 or 4096
×
18
‘Synchronous’ Enable-Plus-Clock Control at Both
Input Port and Output Port
Independently-Synchronized Operation of Input Port
and Output Port
Control Inputs Sampled on Rising Clock Edge
Most Control Signals Assertive-LOW for
Noise Immunity
May be Cascaded for Increased Depth, or
Paralleled for Increased Width
16 mA-IOL High-Drive Three-State Outputs
Five Status Flags: Full, Almost-Full, Half-Full,
Almost-Empty, and Empty; ‘Almost’ Flags are
Programmable
In Enhanced Operating Mode, Almost-Full,
Half-Full, and Almost-Empty Flags can be Made
Completely Synchronous
In Enhanced Operating Mode, Duplicate Enables
for Interlocked Paralleled FIFO Operation, for
36-Bit Data Width, when Selected and
Appropriately Connected
In Enhanced Operating Mode, Disabling
Three-State Outputs May be Made to Suppress
Reading
Data Retransmit Function
TTL/CMOS-Compatible I/O
Space-Saving 68-Pin PLCC Package; Even-Smaller
64-Pin TQFP Package
RESET
LOGIC
INPUT
PORT
RS
INPUT
PORT
CONTROL
LOGIC
READ
POINTER
WRITE
POINTER
DEDICATED AND
PROGRAMMABLE
STATUS FLAGS
FIFO
MEMORY ARRAY
2048 x 18/4096 x 18
OUTPUT
PORT
CONTROL
LOGIC
FF
PAF
WXO/HF
RXO
/EF
2
PAE
D
0
- D
17
WEN
WCK
Q
0
- Q
17
RCK
OUTPUT
PORT
REN
OE
PROGRAMMABLE
REGISTERS
EXPANSION
LOGIC
WXI/
WEN
2
WXO/HF
RXI/
REN
2
RXO/
EF
2
FL/
RT
LD
540235-1
WXI/
WEN
2
RXI/
REN
2
BOLD ITALIC = Enhanced Operating Mode.
EMODE
EF
Figure 1. LH540235/45 Block Diagram
BOLD ITALIC = Enhanced Operating Mode
1