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參數(shù)資料
| 型號(hào)： | LH540235 |
| 廠商： | Sharp Corporation |
| 英文描述： | 2048 x 18 / 4096 x 18 Synchronous FIFOs |
| 中文描述： | 2048 ×四千零九十六分之十八× 18同步FIFO的 |
| 文件頁(yè)數(shù)： | 13/46頁(yè) |
| 文件大?。?/td> | 369K |
| 代理商： | LH540235 |
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Table 5. Control-Register Format
COMMAND
REGISTER
BITS
CODE
VALUE AFTER RESET
FLAG
AFFECTED,
IF ANY
DESCRIPTION
NOTES
EMODE = H
EMODE = L
00
L
L
H
–
Deassertion of LD does not
reset the programmable-
register write pointer and
read pointer.
Deassertion of LD resets
the programmable-register
write pointer and read
pointer to address Word 0,
the Programmable-Almost-
Empty-Flag-Offset Register.
The change takes effect
after a valid write operation
or a valid read operation,
respectively, to the memory
array.
Set by
↑
RCLK, reset by
↑
WCLK.
Set and reset by
↑
RCLK.
Set by
↑
WCLK, reset by
↑
RCLK.
IDT-compatible addressing
of programmable registers.
H
Non-ambiguous
addressing of
programmable registers.
01
L
L
H
PAE
Asynchronous flag
clocking.
Synchronous flag clocking.
Asynchronous flag
clocking.
Synchronous flag clocking
at output port.
Synchronous flag clocking
at input port.
Asynchronous flag
clocking.
Synchronous flag clocking.
Allows the read-address
pointer to advance even
when Q
0
– Q
17
are not
driving the output bus.
Inhibits the read-address
pointer from advancing
when Q
0
– Q
17
are not
driving the output bus;
thus, guards against data
loss.
Future use to control depth
cascading and interlocked
paralleling.
H
03, 02
LL
LL
HH
HF
LH
Set and reset by
↑
RCLK.
HL,
HH
Set and reset by
↑
WCLK.
04
L
L
H
PAF
Set by
↑
WCLK, reset by
↑
RCLK.
Set and reset by
↑
WCLK.
OE has no effect on an
internal read operation,
apart from disabling the
outputs.
Deassertion of OE inhibits
a read operation; whenever
the data outputs Q
0
– Q
17
are in the high-Z state, the
read pointer does not
advance.
H
05
L
L
H
–
H
06
L
L
L
–
Reserved.
H
11, 10,
09, 08, 07
NOTES:
1.
When
EMODE
is HIGH, and
Control Register bits 00-05 are LOW,
the FIFO behaves in a manner functionally equivalent to the
IDT72235B/45B FIFO of similar depth and speed grade. Under these conditions, the
Control Register
is not visible or accessible to the ex-
ternal system which includes the FIFO.
2.
If
EMODE
is not asserted (is HIGH),
Control Register bits 00-05 remain LOW
after a reset operation.
However, if EMODE is asserted (is
LOW) during a reset operation, Control Register bits 00-05 are forced HIGH, and remain HIGH until changed. Control Register bits
06-11 are unaffected by EMODE.
LLLLL
LLLLL
LLLLL
–
Reserved.
Reserved.
DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES (cont’d)
BOLD ITALIC = Enhanced Operating Mode
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
13
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| LH540235M-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
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| LH540235U-25 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:2048 x 18 / 4096 x 18 Synchronous FIFOs |
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