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參數(shù)資料
| 型號(hào)： | LAN8187 |
| 廠商： | SMSC Corporation |
| 英文描述： | High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX |
| 中文描述： | 高性能信息產(chǎn)業(yè)部及RMII 10/100以太網(wǎng)PHY與HP Auto - MDIX功能 |
| 文件頁(yè)數(shù)： | 51/66頁(yè) |
| 文件大小： | 545K |
| 代理商： | LAN8187 |
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High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
Datasheet
5.4.7
SMSC LAN8187/LAN8187I
51
Revision 0.6 (02-24-06)
DATASHEET
LED Description
The PHY provides four LED signals. These provide a convenient means to determine the mode of
operation of the Phy. All LED signals are either active high or active low.
The four LED signals can be either active-high or active-low. Polarity depends upon the Phy address
latched in on reset. The LAN8187/LAN8187I senses each Phy address bit and changes the polarity of
the LED signal accordingly. If the address bit is set as level “1”, the LED polarity will be set to an active-
low. If the address bit is set as level “0”, the LED polarity will be set to an active-high.
The ACTIVITY LED output is driven active when CRS is active (high). When CRS becomes inactive,
the Activity LED output is extended by 128ms.
The
LINK LED output is driven active whenever the PHY detects a valid link. The use of the 10Mbps
or 100Mbps link test status is determined by the condition of the internally determined speed selection.
The SPEED100 LED output is driven active when the operating speed is 100Mbit/s or during Auto-
negotiation. This LED will go inactive when the operating speed is 10Mbit/s or during line isolation
(register 31 bit 5).
The Full-Duplex LED output is driven active low when the link is operating in Full-Duplex mode.
5.4.8
Loopback Operation
The 10/100 digital has two independent loop-back modes: Internal loopback and far loopback.
5.4.8.1
Internal Loopback
The internal loopback mode is enabled by setting bit register 0 bit 14 to logic one. In this mode, the
scrambled transmit data (output of the scrambler) is looped into the receive logic (input of the
descrambler). The COL signal will be inactive in this mode, unless collision test (bit 0.7) is active.
In this mode, during transmission (TX_EN is HIGH), nothing is transmitted to the line and the
transmitters are powered down.
5.4.9
Configuration Signals
The PHY has 11 configuration signals whose inputs should be driven continuously, either by external
logic or external pull-up/pull-down resistors.
5.4.9.1
Physical Address Bus - PHYAD[4:0]
The PHYAD[4:0] signals are driven high or low to give each PHY a unique address. This address is
latched into an internal register at end of hardware reset. In a multi-PHY application (such as a
repeater), the controller is able to manage each PHY via the unique address. Each PHY checks each
management data frame for a matching address in the relevant bits. When a match is recognized, the
PHY responds to that particular frame. The PHY address is also used to seed the scrambler. In a multi-
PHY application, this ensures that the scramblers are out of synchronization and disperses the
electromagnetic radiation across the frequency spectrum.
5.4.9.2
Mode Bus – MODE[2:0]
The MODE[2:0] bus controls the configuration of the 10/100 digital block.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LAN8187_06 | 制造商:SMSC 制造商全稱:SMSC 功能描述:【15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWRTM |
| LAN8187I | 制造商:SMSC 制造商全稱:SMSC 功能描述:High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX |
| LAN8187I-JT | 功能描述:以太網(wǎng) IC HiPerfrm Ethrnt PHY RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN8187-JT | 功能描述:以太網(wǎng) IC HiPerfrm Ethrnt PHY RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN83C171 | 制造商:SMSC 制造商全稱:SMSC 功能描述:EPIC/XF ACPI/PC 97 Compliant Integrated PCI 10/100 Mbps Fast Ethernet Controller |
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