參數(shù)資料
型號(hào)： LAN8187
廠(chǎng)商： SMSC Corporation
英文描述： High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
中文描述： 高性能信息產(chǎn)業(yè)部及RMII 10/100以太網(wǎng)PHY與HP Auto - MDIX功能
文件頁(yè)數(shù)： 48/66頁(yè)
文件大?。?/td> 545K
代理商： LAN8187
High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
Datasheet
Revision 0.6 (02-24-06)
48
SMSC LAN8187/LAN8187I
DATASHEET
5.3
Interrupt Management
The Management interface supports an interrupt capability that is not a part of the IEEE 802.3
specification. It generates an active low interrupt signal on the nINT output whenever certain events
are detected. Reading the Interrupt Source register (Register 29) shows the source of the interrupt,
and clears the interrupt output signal. The Interrupt Mask register (Register 30) enables for each
source to set (LOW) the nINT, by asserting the corresponding mask bit. The Mask bit does not mask
the source bit in register 29. At reset, all bits are masked (negated). The nINT is an asynchronous
output.
31.11
MII_CLK_SEL
MII Mode:
0 = MII Clock of 25MHz. (Default)
1 = Can be written in MII mode to set the interface
speed to 50MHz.
RMII Mode:
0 = Invalid (Do not clear this bit if in RMII mode)
1 = RMII Clock of 50 MHz (Default)
Note:
Defaults low (0) always in MII mode and high
always in RMII mode.
RW
RMII/MII
mode
depnd’t
31.10
Reserved
Reserved
RW
0
31.9:7
GPO[2:0]
General Purpose Output connected to signals
GPO[2:0]
RW
0
31.6
Enable 4B5B
0 = Bypass encoder/decoder.
1 = enable 4B5B encoding/decoding.
MAC Interface must be configured in MII mode.
RW
1
31.5
Reserved
Write as 0, ignore on Read.
RW
0
31.4:2
Speed Indication
HCDSPEED value:
[001]=10Mbps Half-duplex
[101]=10Mbps Full-duplex
[010]=100Base-TX Half-duplex
[110]=100Base-TX Full-duplex
RO
000
31.1
Reserved
Write as 0; ignore on Read
RW
0
31.0
Scramble Disable
0 = enable data scrambling
1 = disable data scrambling,
RW
0
INTERRUPT SOURCE
SOURCE/MASK REG BIT #
ENERGYON activated
7
Auto-Negotiate Complete
6
Remote Fault Detected
5
Link Status negated (not asserted)
4
Auto-Negotiation LP Acknowledge
3
Parallel Detection Fault
2
Auto-Negotiation Page Received
1
Table 5.44 Register 31 - PHY Special Control/Status (continued)
ADDRESS
NAME
DESCRIPTION
MODE
DEFAULT
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