參數(shù)資料
型號(hào)： LAN8187-JT
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
英文描述： High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
中文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64
文件頁(yè)數(shù)： 64/66頁(yè)
文件大?。?/td> 545K
代理商： LAN8187-JT
High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
Datasheet
Revision 0.6 (02-24-06)
64
SMSC LAN8187/LAN8187I
DATASHEET
Note 6.1
These levels apply when a 0-3.3V Clock is driven into CLKIN/XTAL1 and XTAL2 is floating.
The maximum input voltage on XTAL1 is VDDIO + 0.4V.
Table 6.17 General Signals
NAME
V
IH
V
IL
I
OH
I
OL
V
OL
V
OH
GPO0
-8 mA
+8 mA
+0.4 V
VDDIO – +0.4 V
GPO1
-8 mA
+8 mA
+0.4 V
3.7 V
GPO2
-8 mA
+8 mA
+0.4 V
VDDIO – +0.4 V
nRST
VDDIO – +0.4 V
+0.5 V
CLKIN/XTAL1
Note 6.1
+1.40 V
+0.5 V
XTAL2
-
-
NC
Table 6.18 Analog References
NAME
BUFFER TYPE
V
IH
V
IL
I
OH
I
OL
V
OL
V
OH
EXRES1
AI
NC
AI/O
Table 6.19 Internal Pull-Up / Pull-Down Configurations
NAME
PULL-UP OR PULL-DOWN
GPO0/MII
Pull-down
GPO1/PHYAD4
Pull-up
MODE0
Pull-up
MODE1
Pull-up
MODE2
Pull-up
TEST0
Pull-down
TEST1
Pull-down
SPEED100/PHYAD0
Pull-up
LINK/PHYAD1
Pull-up
ACTIVITY/PHYAD2
Pull-up
FDUPLEX//PHYAD3
Pull-up
nINT/TX_ER/TXD4
Pull-up
nRST
Pull-up
MDIO
Pull-down
MDC
Pull-down
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