參數(shù)資料
型號(hào)： LAN8187-JT
廠商： STANDARD MICROSYSTEMS CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
中文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64
文件頁(yè)數(shù)： 26/66頁(yè)
文件大小： 545K
代理商： LAN8187-JT
High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
Datasheet
Revision 0.6 (02-24-06)
26
SMSC LAN8187/LAN8187I
DATASHEET
It uses LVCMOS signal levels, compatible with common digital CMOS ASIC processes
The RMII includes 6 interface signals with one of the signals being optional:
transmit data - TXD[1:0]
transmit strobe - TX_EN
receive data - RXD[1:0]
receive error - RX_ER (Optional)
carrier sense - CRS_DV
Reference Clock - CLKIN/XTAL1 (RMII references usually define this signal as REF_CLK)
4.6.2.1
Reference Clock
The Reference Clock - CLKIN, is a continuous clock that provides the timing reference for CRS_DV,
RXD[1:0], TX_EN, TXD[1:0], and RX_ER. The Reference Clock is sourced by the MAC or an external
source. Switch implementations may choose to provide REF_CLK as an input or an output depending
on whether they provide a REF_CLK output or rely on an external clock distribution device.
The “Reference Clock” frequency must be 50 MHz +/- 50 ppm with a duty cycle between 35% and
65% inclusive. The SMSC LAN8187/LAN8187I uses the “Reference Clock” as the network clock such
that no buffering is required on the transmit data path. The SMSC LAN8187/LAN8187I will recover the
clock from the incoming data stream, the receiver will account for differences between the local
REF_CLK and the recovered clock through use of sufficient elasticity buffering. The elasticity buffer
does not affect the Inter-Packet Gap (IPG) for received IPGs of 36 bits or greater. To tolerate the clock
variations specified here for Ethernet MTUs, the elasticity buffer shall tolerate a minimum of +/-10 bits.
4.6.2.2
CRS_DV - Carrier Sense/Receive Data Valid
The CRS_DV is asserted by the LAN8187/LAN8187I when the receive medium is non-idle. CRS_DV
is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode.
That is, in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 non-contiguous
zeroes in 10 bits are detected, carrier is said to be detected.
Loss of carrier shall result in the deassertion of CRS_DV synchronous to the cycle of REF_CLK which
presents the first di-bit of a nibble onto RXD[1:0] (i.e. CRS_DV is deasserted only on nibble
boundaries). If the LAN8187/LAN8187I has additional bits to be presented on RXD[1:0] following the
initial deassertion of CRS_DV, then the LAN8187/LAN8187I shall assert CRS_DV on cycles of
REF_CLK which present the second di-bit of each nibble and de-assert CRS_DV on cycles of
REF_CLK which present the first di-bit of a nibble. The result is: Starting on nibble boundaries
CRS_DV toggles at 25 MHz in 100Mb/s mode and 2.5 MHz in 10Mb/s mode when CRS ends before
RX_DV (i.e. the FIFO still has bits to transfer when the carrier event ends.) Therefore, the MAC can
accurately recover RX_DV and CRS.
During a false carrier event, CRS_DV shall remain asserted for the duration of carrier activity. The data
on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV
is asynchronous relative to REF_CLK, the data on RXD[1:0] shall be “00” until proper receive signal
decoding takes place.
4.6.3
MII vs. RMII Configuration
The LAN8187/LAN8187I must be configured to support the MII or RMII bus for connectivity to the
MAC. This configuration is done through the GPO0/MII pin.
MII or RMII mode selection is latched on the rising edge of the internal reset (nreset) based on the
strapping of the GPO0/MII pin. To select MII mode, float the GPO0/MII pin. To select RMII mode, pull-
high with an external resistor (see
Table 4.3, “Boot Strapping Configuration Resistors,” on page 32
) to
VDD33.
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