參數(shù)資料
型號： LAN8187-JT
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
英文描述： High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
中文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64
文件頁數(shù)： 31/66頁
文件大小： 545K
代理商： LAN8187-JT
High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
Datasheet
SMSC LAN8187/LAN8187I
31
Revision 0.6 (02-24-06)
DATASHEET
The RXD3 pin is latched on the rising edge of the internal reset (nreset) to select the mode. The
system designer must float the RXD3 pin for nINT mode or pull-low with an external resistor (see
Table 4.3, “Boot Strapping Configuration Resistors,” on page 32
) to VSS to set the device in
TX_ER/TXD4 mode. The default setting is high (nINT mode).
Note:
For VDDIO operation below +2.5V, SMSC recommends designs add external strapping
resistors in addition the internal strapping resistors to ensure proper strapped operation.
4.11
PHY Address Strapping and LED Output Polarity Selection
The PHY ADDRESS bits are latched on the rising edge of the internal reset (nreset). The 5-bit address
word[0:4] is input on the LED1, LED2, LED3, LED4, GPO1 output pins. The default setting is all high
5'b1_1111.
The address lines are strapped as defined in the diagram below. The LED outputs will automatically
change polarity based on the presence of an external pull-down resistor. If the LED pin is pulled high
(by an internal 100K pull-up resistor) to select a logical high PHY address, then the LED output will
be active low. If the LED pin is pulled low (by an external pull-down resistor (see
Table 4.3, “Boot
Strapping Configuration Resistors,” on page 32
) to select a logical low PHY address, the LED output
will then be an active high output.
To set the PHY address on the LED pins without LEDs or on the GPO1 or CRS pin, float the pin to
set the address high or pull-down the pin with an external resistor (see
Table 4.3, “Boot Strapping
Configuration Resistors,” on page 32
) to GND to set the address low. See the figure below:
Figure 4.5 PHY Address Strapping on LED’s
4.12
Variable Voltage I/O
The Digital I/O pins on the LAN8187/LAN8187I are variable voltage to take advantage of low power
savings from shrinking technologies. These pins can operate from a low I/O voltage of +1.6V up to
+3.6V. Due to this low voltage feature addition, the system designer needs to take consideration as
for two aspects of their design. Boot strapping configuration and I/O voltage stability.
LED1-LED4
~270 ohms
Phy Address = 0
LED output = active high
~10K ohms
~270 ohms
LED1-LED4
VDD
Phy Address = 1
LED output = active low
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