參數(shù)資料
型號(hào)： LAN8187-JT
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
英文描述： High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
中文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64
文件頁(yè)數(shù)： 15/66頁(yè)
文件大?。?/td> 545K
代理商： LAN8187-JT
High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
Datasheet
SMSC LAN8187/LAN8187I
15
Revision 0.6 (02-24-06)
DATASHEET
MODE2
I
PHY Operating Mode Bit 2:
set the default MODE of the PHY.
See
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 51
, for
the MODE options.
MODE1
I
PHY Operating Mode Bit 1:
set the default MODE of the PHY.
See
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 51
, for
the MODE options.
MODE0
I
PHY Operating Mode Bit 0:
set the default MODE of the PHY.
See
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 51
, for
the MODE options.
TEST1
I
Test Mode Select 1:
Must be left floating.
TEST0
I
Test Mode Select 0:
Must be left floating.
REG_EN
I
Regulator Enable
: Internal +1.8V regulator enable:
VDDIO – Enables internal regulator.
VSS– Disables internal regulator.
AMDIX_EN
I
HP Auto-MDIX Enable:
Auto-MDIX mode enable.
+3.3V – Enables HP Auto-MDIX.
0V – Disables HP Auto-MDIX
CH_SELECT
I
Channel Select:
With Auto-MDIX disabled above,
VDDIO – Enables HP Auto-MDIX.
0V – Disables HP Auto-MDIX
GPO0/MII
I/O
General Purpose Output 0 –
General Purpose Output signal.
Driven by bits in registers 27 and 31.
MII –
MII/RMII mode selection is latched on the rising edge of
the internal reset (nreset) based on the following strapping:
Float the GPO0 pin for MII mode or pull-high with an external
Pull-up resistor (see
Table 4.3, “Boot Strapping Configuration
Resistors,” on page 32
) to VDDIO to set the device in RMII
mode.
Note:
See
Section 4.6.3, "MII vs. RMII Configuration," on
page 26
for more details.
a.On nRST transition high, the PHY latches the state of the configuration pins in this table.
Table 3.5 General Signals
SIGNAL NAME
TYPE
DESCRIPTION
nINT
I/O
LAN Interrupt
– Active Low output. Place a pull-up external
resistor (see
Table 4.3, “Boot Strapping Configuration Resistors,”
on page 32
) to VCC 3.3V.
Notes:
This signal is mux’d with TX_ER/TXD4
See
Section 4.10, "(TX_ER/TXD4)/nINT Strapping," on
page 30
for additional details on Strapping options.
nRST
I
External Reset
– input of the system reset. This signal is active
LOW.
Table 3.4 Boot Strap Configuration Inputs
a
SIGNAL NAME
TYPE
DESCRIPTION
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