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參數(shù)資料
| 型號： | LAN8187-JT |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64 |
| 文件頁數(shù)： | 12/66頁 |
| 文件大?。?/td> | 545K |
| 代理商： | LAN8187-JT |
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High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
Datasheet
Revision 0.6 (02-24-06)
12
SMSC LAN8187/LAN8187I
DATASHEET
Chapter 3 Pin Description
This chapter describes the signals on each pin. When a lower case “n” is used at the beginning of the
signal name, it indicates that the signal is active low. For example, nRST indicates that the reset signal
is active low.
3.1
I/O Signals
I
Input. Digital LVCMOS levels.
O
Output. Digital LVCMOS levels.
I/O
Input or Output. Digital LVCMOS levels.
Note:
The digital signals are not 5V tolerant. The are variable voltage from +1.6V to +3.6V.
AI
Input. Analog levels.
AO
Output. Analog levels.
Table 3.1 MII Signals
SIGNAL NAME
TYPE
DESCRIPTION
TXD0
I
Transmit Data 0
: Bit 0 of the 4 data bits that are accepted by
the PHY for transmission.
TXD1
I
Transmit Data 1
: Bit 1 of the 4 data bits that are accepted by
the PHY for transmission.
TXD2
I
Transmit Data 2
: Bit 2 of the 4 data bits that are accepted by
the PHY for transmission
Note:
This signal should be grounded in RMII Mode.
TXD3
I
Transmit Data 3
:
Bit 3 of the 4 data bits that are accepted by
the PHY for transmission.
Note:
This signal should be grounded in RMII Mode
nINT/
TX_ER/
TXD4
I/O
MII Transmit Error
: When driven high, the 4B/5B encode
process substitutes the Transmit Error code-group (/H/) for the
encoded data word. This input is ignored in 10Base-T operation.
MII Transmit Data 4:
In Symbol Interface (5B Decoding) mode,
this signal becomes the MII Transmit Data 4 line, the MSB of the
5-bit symbol code-group.
Notes:
This signal is not used in RMII Mode.
This signal is mux’d with nINT
See
Section 4.10, "(TX_ER/TXD4)/nINT Strapping," on
page 30
for additional information on configuration/strapping
options.
TX_EN
I
Transmit Enable
: Indicates that valid data is presented on the
TXD[3:0] signals, for transmission. In RMII Mode, only TXD[1:0]
have valid data.
TX_CLK
O
Transmit Clock
: 25MHz in 100Base-TX mode. 2.5MHz in
10Base-T mode.
Note:
This signal is not used in RMII Mode
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