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參數(shù)資料
| 型號： | LAN8187-JT |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64 |
| 文件頁數(shù)： | 45/66頁 |
| 文件大?。?/td> | 545K |
| 代理商： | LAN8187-JT |
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High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
Datasheet
SMSC LAN8187/LAN8187I
45
Revision 0.6 (02-24-06)
DATASHEET
17.9
FARLOOPBACK
Force the module to the FAR Loop Back mode, i.e. all
the received packets are sent back simultaneously (in
100Base-TX only). This bit is only active in RMII
mode. In this mode the user needs to supply a 50MHz
clock to the PHY. This mode works even if MII Isolate
(0.10) is set.
RW
0
17.8
FASTEST
Auto-Negotiation Test Mode
0 = normal operation
1 = activates test mode
RW
0
17.7:5
Reserved
Write as 0, ignore on read.
17.4
REFCLKEN
1= Enables special filtering using a 50 MHz Clock in
10Base-T mode.
RW
0
17.3
PHYADBP
1 = PHY disregards PHY address in SMI access
write.
RW
0
17.2
Force
Good Link Status
0 = normal operation;
1 = force 100TX- link active;
Note:
This bit should be set only during lab testing
RW
0
17.1
ENERGYON
ENERGYON – indicates whether energy is detected
on the line (see
Section 5.4.5.2, "Energy Detect
Power-Down," on page 50
); it goes to “0” if no valid
energy is detected within 256ms. Reset to “1” by
hardware reset, unaffected by SW reset.
RO
1
17.0
Reserved
Write as “0”. Ignore on read.
RW
0
Table 5.39 Register 18 - Special Modes
ADDRESS
NAME
DESCRIPTION
MODE
DEFAULT
18.15:14
MIIMODE
MII Mode
: set the mode of the MII:
0 – MII interface.
1 – RMII interface
RW,
NASR
18.13
CLKSELFREQ
Clock In Selected Frequency. Set the requested input
clock frequency. This bit drives signal that goes to
external logic of the Phy and select the desired
frequency of the input clock:
0 – the clock frequency is 25MHz
1 – Reserved
RO,
NASR
18.12
DSPBP
DSP Bypass mode. Used only in special lab tests.
RW,
NASR
0
18.11
SQBP
SQUELCH Bypass mode.
RW,
NASR
0
18.10
Reserved
RW,
NASR
18.9
PLLBP
PLL Bypass mode.
RW,
NASR
18.8
ADCBP
ADC Bypass mode.
RW,
NASR
Table 5.38 Register 17 - Mode Control/Status (continued)
ADDRESS
NAME
DESCRIPTION
MODE
DEFAULT
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