
Table 5:
Control Register.
Ctrl
Bit #
0
Signal
Name
Ext/Int
Control Function Description
Logic
Default
State
0
Determines whether the once-per-
revolution signal (used as the motor’s
feedback for speed) comes from internally
generated source or isto be supplied
externally as an input.
When enabled, passes external PLL fref to
Phase Detector
Two bits that set the Lock Signal threshold
in the PhaseDetector
0 = Use Int
Speed Fdbk
1 = Use Ext
Speed Fdbk
0 = Enable
1 = Disable
Refer to Table 7
1
Fref Enable
0
2
Lock_
Thrsh_0
Lock_
Thrsh_1
Linear
Out_Ena
1
3
1
4
5
Not used.
Enables Output Drivers. When this signal is
used to Tri-Statethe outputs, it also resets
the resynchronization algorithm.
This bit along with the
OUTPUT ENABLE
pin forms a logical AND function.
When brought high, initiates the Align and
Go algorithm. When low, Brakeaction
occurs after the Brake Delay Timeout.
This bit along with the RUN/BRAKE pin
forms a logical AND function.
Resets the sequencer to Phase 1. Reset
when in Brake Mode.
Selects either the Internal Auto Start-Up or
External Algorithm.
Increments sequencer
0 = Required
0 = Enable
1 = Disable
0
1
6
Run/Brake
1 = Run
0 = Brake
1
7
Seq_Reset
1 = Reset
0 = Normal
1 = Auto
0 = External
1 = Mask Bemf
0 = Normal
Refer to Table 6
0
8
Auto/Ext
1
9
Seq_Incr
0
10
Phase_
Delay_0
Phase_
Delay_1
Phase_
Delay_2
Auto_Str_
Dly_0
Auto_Str_
Dly_1
Ilim_Gain
Three bits that set the Delay between the
detection of the Bemf zero crossing and
the commutation to the next phase.
1
11
0
12
1
13
These 2 Bits define 4 possibledelayes for
Auto Start-Up Algorithm.
Refer to Table 8
1
14
1
15
Programs the I Limit for either the value set
by
ILIM SET
or /2
0 = Ilimit
1 = Ilimit/2
0
L6238
31/35