![](http://datasheet.mmic.net.cn/370000/L6238_datasheet_16703397/L6238_30.png)
Table 5 lists the 16 available control bits along
with a description and power up default values.
Certain bits are replications of their external pin
counterparts while others provide the means to
”customize” the controller to match a unique ap-
plication and are described in further detail below.
Phase Delay - A more efficient torque profile
can be achieved by advancing the commuta-
tion angle to compensatefor the L/R time con-
stant. There are 3 bits in the serial port that are
used to program the delay between the zero-
crossing and the commutation point. Thus the
user has the ability to use the motor more effi-
ciently by programming the optimal delay. Ta-
ble 6 is a mappingbetween the serial ports bits
and the commutationdelay.
In selecting the phase delay, the amount of
slew rate introducedmust be considered,since
the switching is effectively at the 50% points
and thisdelay can be a significantcontribution.
Lock Threshold - Bits 2 and 3 control the
phase error window between the reference
and the motor that must be met in order to al-
low the
LOCK
signalto go high. Four differenct
thresholds cover the range between 6.4 and
51.2us as shown in Table7.
Auto Start Delay - Table 8 lists the delays
available for the Align & Go start up algorithm
withvalues for 90Hzand 60Hz applications.
6.6 Status Register
The serial port also contains16 bits that give use-
ful information about the inner workings of the
controller. Table 9 provides a functional descrip-
tion of each of the status bits. The status bits
prove valuable during certain situations with one
examplehighlitedbelow.
Align +Go - These 2 bits can be used to deter-
mine if a resync operation was succesful or
not. During a commanded resync, these bits
will be initially high, and will stay high if the
resync was successful. However, figure 34
shows the timing of these 2 bits during an un-
succesful resync where the Go bit goes low
419 ms after the resync command if no Bemf
zerocrossing is detected.
Figure34:
Failed Rysync.
Tasd <1>
0
0
1
1
Tasd <0>
0
1
0
1
Ta
Tg
Ts
0.178 s
0.256 s
0.533 s
0.711 s
0.711 s
1.422 s
2.133 s
2.844 s
0.419 s
0.419 s
0.419 s
0.419 s
Note: PLL Reference Frequency = 90Hz
System Clock = 10MHz.
L6238
30/35