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參數(shù)資料
| 型號： | L6238 |
| 廠商： | 意法半導體 |
| 英文描述： | Sensorless Spindle Motor Driver(無傳感器主軸電機驅(qū)動器) |
| 中文描述： | 傳感器主軸電機驅(qū)動器（無傳感器主軸電機驅(qū)動器） |
| 文件頁數(shù)： | 21/35頁 |
| 文件大?。?/td> | 383K |
| 代理商： | L6238 |
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lower drivers in a brake mode if the analog supply
is lost.
Figure 17 is a simplified schematic of the charge
pump circuitry. A capacitor, C
pump
, is used to re-
trieve energy from the analog supply and then
”pumps” it into the storagecapacitor, C
resvr
. An in-
ternal 300kHz oscillator first turns ON Q2 to
quickly charge C
pump
to approximately the rail
voltage. The oscillator then turns ON Ql while
turning OFF Q2. Since the bottom plate of C
pump
is now effectively at the rail potential, C
resvr
is
charged to ~ twice the rail voltage viaD2. A zener
referenced series-pass regulator supplies a volt-
age,V
brake
, duringbrake mode.
5.4 Output Current Control
The output current is controlled in a linear fashion
via a transconductance loop. Referring to figure
18, the sourcing FET of one phase is forced into
full conduction by connecting the gate to V
pump
,
while the sinking transistor of an appropriate
phase operates as a transconductance element.
To understand the current control loop, it will be
assumed that Q2 in figure 18 is enabled via SW2
by the sequencer.
During a run condition, the current in Q2 is moni-
tored by a resistor R
4
connectedto the R
sense
in-
put. The resulting voltage that appears across R4
is amplified by a factorof four by A3 and is sent to
A2 where it is compared to the PLL error signal.
A2 provides sufficient drive to Q2 in order to
maintain the motor speed at the proper level as
commanded by the PLL.
During initial start-up, the error signal from the
output of the PLL Phase/Frequency Detector will
be at compliancein order to quickly bring the mo-
tor up to correct speed. The motor current during
this condition can be safely limited to a predeter-
mined value by applying a voltage to the ILIM
SET input.
The voltage at this input is buffered by A1 and
sent to multiplexer, SWl. The output voltage of the
multiplexer, Vclmp, is used to control the maxi-
mum non-inverting input voltage for amplifier A2.
This multiplexer also receives a voltagethat is 1/2
the
ILIM SET
value via a resistor divider con-
nected to the buffer. Control bit llim Gain deter-
mines which voltage is available at the output of
the multiplexer and allows a 2:1 change in the
output current limit under softwarecontrol.
For example, if the Ilim Gain control bit is set
high, and 3.3V were applied to the
ILIM SET
in-
put, then V
clmp
would equal 1.65V. Since A3 has
a voltagegain of 4, this would translateto a maxi-
mum sensed voltage at the R
sense
input equal to
0.41V. If Rslew were selected to be 0.33
, then
the maximum output current would be limited to
~1.25A.
By setting the Ilim Gaincontrol bit low, Vclmp now
equals ILIM SET, and the clamped sensed volt-
age at the R
sense
input would be doubled to
0.82V,allowing a maximum of 2.5A at the output.
Figure17:
ChargePump Circuit.
L6238
21/35
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