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參數(shù)資料
| 型號(hào)： | L6238 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Sensorless Spindle Motor Driver(無傳感器主軸電機(jī)驅(qū)動(dòng)器) |
| 中文描述： | 傳感器主軸電機(jī)驅(qū)動(dòng)器（無傳感器主軸電機(jī)驅(qū)動(dòng)器） |
| 文件頁數(shù)： | 16/35頁 |
| 文件大小： | 383K |
| 代理商： | L6238 |
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3)
Phase Lock
- After a brief settling time, typi-
cally 1-2 seconds after spin-up, the counters will
alternately count up and down as required to
maintain the phase difference to be as close to
minimum as possible. The counter outputs at this
time shouldbe ”hovering” around 10000000.
The outputs of the two DACs are sent to latches
that store the digital representation of the meas-
ured phase error. This information is then bussed
to the DACs.
4.3 Coarse/FineDACs
Two DACs are used to convert the digital phase
error information into an analog voltage that can
Table 2
be used to command the output driver’s current.
In figure 12, the two 8-bit digital error signals are
used to switch in 256 possible voltages derived
from a precision Band-Gap reference. The same
resistor ladder string is used for the Coarse and
Fine DACs. The outputs of the DACS are then
sent to buffer stages and added together via a
summingamplifier.
4.4 Transfer Functions
Figure 13 represent the Output Voltage vs Phase
Error for the Coarse and Fine DACs depicting the
resolutionthat is achievable.
Table 2 shows examples of the resolution of both
Figure12:
Coarseand FineDAC’s.
Fsystem
Clock
8MHz
10MHz
12MHz
Fcoarse
Phase LSB
Coarse
64.1
μ
s
51.3
μ
s
42.7
μ
s
(Range)
Coarse
16.3ms
13.1ms
10.9ms
Ffine
Phase LSB
Fine
1.0
μ
s
800ns
667ns
(Range)
Fine
255
μ
s
204
μ
s
170
μ
s
15.6KHz
19.5KHz
23.4KHz
1.0MHz
1.25MHz
1.5MHz
L6238
16/35
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