參數(shù)資料
型號: KM44S4020CT
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 2M x 4Bit x 2 Banks Synchronous DRAM(2M x 4位 x 2組同步動態(tài)RAM)
中文描述: 2米x 4位× 2銀行同步DRAM(2米× 4位× 2組同步動態(tài)RAM)的
文件頁數(shù): 17/44頁
文件大?。?/td> 604K
代理商: KM44S4020CT
CMOS SDRAM
DEVICE OPERATIONS - I
ELECTRONICS
REV. 4 Feb. '98
1) Clock Suspended During Write (BL=4)
1. CLOCK Suspend
WR
D
0
D
1
D
2
D
3
D
0
D
1
D
2
D
3
CLK
CMD
CKE
Internal
CKE
DQ(CL2)
DQ(CL3)
Masked by CKE
2) Clock Suspended During Read (BL=4)
D
0
Q
1
Not Written
1) Write Mask (BL=4)
2. DQM Operation
WR
D
0
D
1
D
3
D
0
D
1
D
3
CLK
CMD
DQM
DQ(CL2)
DQ(CL3)
Masked by DQM
2) Read Mask (BL=4)
RD
Q
0
Q
2
Q
3
Q
1
Q
2
Q
3
Masked by DQM
DQM to Data-in Mask = 0
DQM to Data-out Mask = 2
Hi-Z
Hi-Z
3) DQM with Clock Suspended (Full Page Read)
CLK
Note 2
RD
CMD
CKE
DQ(CL2)
DQ(CL3)
Q
0
Q
4
Q
7
Q
8
Q
2
Q
3
Q
6
Q
7
Q
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQM
*Note :
1. CKE to CLK disable/enable = 1CLK.
2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L"
3. DQM masks both data-in and data-out.
BASIC FEATURE AND FUNCTION DESCRIPTIONS
RD
Q
0
Q
2
Q
0
Q
1
Q
2
Q
3
Masked by CKE
Q
3
Suspended Dout
Q
6
Q
5
相關(guān)PDF資料
PDF描述
KM44S64230A 16M x 4Bit x 4 Banks Synchronous DRAM(16M x 4位 x 4組同步動態(tài)RAM)
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