參數(shù)資料
型號: KM44S64230A
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 16M x 4Bit x 4 Banks Synchronous DRAM(16M x 4位 x 4組同步動態(tài)RAM)
中文描述: 16米x 4位× 4銀行同步DRAM(16米x 4位× 4組同步動態(tài)RAM)的
文件頁數(shù): 1/8頁
文件大?。?/td> 62K
代理商: KM44S64230A
KM44S64230A
CMOS SDRAM
REV. 0 May '98
Preliminary
The KM44S64230A is 268,435,456 bits synchronous high data
rate Dynamic RAM organized as 4 x 16,785,216 words by 4
bits, fabricated with SAMSUNG's high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programma-
ble burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock.
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (8K cycle)
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
16M x 4Bit x 4 Banks Synchronous DRAM
ORDERING INFORMATION
Part No.
Max Freq.
125MHz
100MHz
100MHz
100MHz
Interface
Package
KM44S64230AT-G/F8
KM44S64230AT-G/FH
KM44S64230AT-G/FL
KM44S64230AT-G/F10
LVTTL
54pin
TSOP(II)
Samsung Electronics reserves the right to
change products or specification without
notice.
*
Bank Select
Data Input Register
16M x 4
16M x 4
S
O
I
Column Decoder
Latency & Burst Length
Programming Register
A
R
R
R
C
L
L
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
16M x 4
16M x 4
Timing Register
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