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參數(shù)資料
| 型號(hào)： | K4S161622D |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512K x 16Bit x 2 Banks Synchronous DRAM |
| 中文描述： | 為512k × 16 × 2銀行同步DRAM |
| 文件頁(yè)數(shù)： | 5/41頁(yè) |
| 文件大?。?/td> | 1127K |
| 代理商： | K4S161622D |
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K4S161622D
CMOS SDRAM
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V
*2
, T
A
= 0 to 70
°
C)
Parameter
Value
Unit
Input levels (Vih/Vil)
2.4 / 0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr / tf = 1 / 1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
3.3V
1200
870
Output
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Vtt=1.4V
50
Output
Z0=50
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
1. The DC/AC Test Output Load of K4S161622D-55/60/70 is 30pF.
2. The VDD condition of K4S161622D-55/60 is 3.135V~3.6V.
Note :
50pF
*2
50pF
*1
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following clock unit based AC conversion table
Notes :
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
-70
3
7
2
3
3
7
100
Unit
Note
-55
-60
-80
-10
CAS Latency
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
CL
3
2
-
3
6
2
-
2
3
8
2
3
10
2
CLK
ns
CLK
CLK
CLK
CLK
us
t
CC(min)
t
RRD(min)
t
RCD(min)
t
RP(min)
t
RAS(min)
t
RAS(max)
5.5
8.7
10
12
1
1
1
1
3
3
7
-
-
-
3
3
7
-
-
-
2
2
5
3
3
6
2
2
5
2
2
5
2
2
4
Row active time
Row cycle time
t
RC
(
min
)
10
-
10
-
10
7
9
7
7
6
CLK
1
Last data in to row precharge
Last data in to new col.address delay
Last data in to burst stop
Col. address to col. address delay
Mode Register Set cycle time
t
RDL(min)
t
CDL(min)
t
BDL(min)
t
CCD(min)
t
MRS(min)
1
1
1
1
2
2
1
CLK
CLK
CLK
CLK
CLK
2,
5
2
2
Number of valid output data
CAS Latency=3
CAS Latency=2
ea
4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4S161622E | 1M x 16 SDRAM |
| K4S161622E-TC10 | 1M x 16 SDRAM |
| K4S161622E-TC55 | 1M x 16 SDRAM |
| K4S161622E-TC60 | 1M x 16 SDRAM |
| K4S161622E-TC70 | 1M x 16 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4S161622D-TC/L10 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:512K x 16Bit x 2 Banks Synchronous DRAM |
| K4S161622D-TC/L55 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:512K x 16Bit x 2 Banks Synchronous DRAM |
| K4S161622D-TC/L60 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:512K x 16Bit x 2 Banks Synchronous DRAM |
| K4S161622D-TC/L70 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:512K x 16Bit x 2 Banks Synchronous DRAM |
| K4S161622D-TC/L80 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:512K x 16Bit x 2 Banks Synchronous DRAM |
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