參數(shù)資料
型號(hào): K4S161622D
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512K x 16Bit x 2 Banks Synchronous DRAM
中文描述: 為512k × 16 × 2銀行同步DRAM
文件頁(yè)數(shù): 28/41頁(yè)
文件大?。?/td> 1127K
代理商: K4S161622D
CMOS SDRAM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
K4S161622D
Page Read & Write Cycle at Same Bank @Burst Length=4
HIGH
Row Active
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note :
1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, t
RDL
before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
Read
(A-Bank)
tRCD
*Note 2
tRDL
*Note 1
*Note 3
tCDL
Qa0
Qa1
Qb0
Qb1
Qb2
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
Dc0
Dc1
Dd0
Dd1
Write
(A-Bank)
BA
A
10
/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
Ra
Ca0
Cb0
Cc0
Cd0
Ra
相關(guān)PDF資料
PDF描述
K4S161622E 1M x 16 SDRAM
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