參數(shù)資料
型號(hào)： ISP1563BM,557
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁數(shù)： 80/102頁
文件大?。?/td> 466K
代理商： ISP1563BM,557
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
79 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
15 to 14
PIC[1:0]
Port Indicator Control: Default = 0. Writing to this eld has no effect if P_INDICATOR (bit 16) in
the HCSPARAMS register is logic 0. If P_INDICATOR is logic 1, then the bit encoding is:
00b — Port indicators are off
01b — Amber
10b — Green
11b — Undened
For a description on how these bits are implemented, refer to
Universal Serial Bus Specication
Rev. 2.0.[1]
13
PO
Port Owner: Default = 1. This bit unconditionally goes to logic 0 when CF (bit 0) in the
CONFIGFLAG register makes logic 0 to logic 1 transition. This bit unconditionally goes to logic 1
when the CF bit is logic 0. The system software uses this eld to release ownership of the port to
a selected Host Controller, if the attached device is not a high-speed device. Software writes
logic 1 to this bit, if the attached device is not a high-speed device. Logic 1 in this bit means that a
companion Host Controller owns and controls the port.
12
PP
Port Power: The function of this bit depends on the value of PPC (bit 4) in the HCSPARAMS
register.
If PPC = 0 and PP = 1 — The Host Controller does not have port power control switches. Always
powered.
If PPC = 1 and PP = 1 or 0 — The Host Controller has port power control switches. This bit
represents the current setting of the switch: logic 0 = off, logic 1 = on. When PP is logic 0, the port
is nonfunctional and will not report any status.
When an overcurrent condition is detected on a powered port and PPC is logic 1, the PP bit in
each affected port may be changed by the Host Controller from logic 1 to logic 0, removing power
from the port.
11 to 10
LS[1:0]
Line Status: This eld reects the current logical levels of the DP (bit 11) and DM (bit 10) signal
lines. These bits are used to detect low-speed USB devices before the port reset and enable
sequence. This eld is valid only when the Port Enable bit is logic 0, and the Current Connect
Status bit is set to logic 1.
00b — SE0: Not a low-speed device, perform EHCI reset
01b — K-state: Low-speed device, release ownership of port
10b — J-state: Not a low-speed device, perform EHCI reset
11b — Undened: Not a low-speed device, perform EHCI reset
If bit PP is logic 0, this eld is undened.
9
reserved
-
Table 119. PORTSC 1, 2, 3, 4 - Port Status and Control, 1, 2, 3, 4 register bit description …continued
Address: Content of the base address register + 64h + (4
× Port Number 1) where Port Number is 1, 2, 3, 4
Bit
Symbol
Description
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