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| 型號： | ISP1563BM,557 |
| 廠商： | ST-ERICSSON |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100 |
| 文件頁數(shù)： | 13/102頁 |
| 文件大?。?/td> | 466K |
| 代理商： | ISP1563BM,557 |
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ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
18 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
Table 7.
CMD - Command register (address 04h) bit description
Bit
Symbol
Description
15 to 10
reserved
-
9
FBBE
Fast Back-to-Back Enable: This bit controls whether a master can do fast back-to-back
transactions to various devices. The initialization software must set this bit if all targets are fast
back-to-back capable.
0 — Fast back-to-back transactions are only allowed to the same agent (value after RST#).
1 — The master is allowed to generate fast back-to-back transactions to different agents.
8
SERRE
SERR# Enable: This bit is an enable bit for the SERR# driver. All devices that have an SERR#
pin must implement this bit. Address parity errors are reported only if this bit and the PER bit are
logic 1.
0 — Disable the SERR# driver.
1 — Enable the SERR# driver.
7
SCTRL
Stepping Control: This bit controls whether a device does address and data stepping. Devices
that never do stepping must clear this bit. Devices that always do stepping must set this bit.
Devices that can do either, must make this bit read and write, and initialize it to logic 1 after
RST#.
6
PER
Parity Error Response: This bit controls the response of a device to parity errors. When the bit is
set, the device must take its normal action when a parity error is detected. When the bit is logic 0,
the device sets DPE (bit 15 in the Status register) when an error is detected, but does not assert
PERR# and continues normal operation. The state of this bit after RST# is logic 0. Devices that
check parity must implement this bit. Devices are required to generate parity, even if parity
checking is disabled.
5
VGAPS
VGA Palette Snoop: This bit controls how Video Graphics Array (VGA) compatible and graphics
devices handle accesses to VGA palette registers.
0 — The device must treat palette write accesses like all other accesses.
1 — Palette snooping is enabled, that is, the device does not respond to palette register writes
and snoops data.
VGA compatible devices should implement this bit.
4
MWIE
Memory Write and Invalidate Enable: This is an enable bit for using the Memory Write and
Invalidate command.
0 — Memory writes must be used instead. State after RST# is logic 0.
1 — Masters may generate the command.
This bit must be implemented by master devices that can generate the Memory Write and
Invalidate command.
3SC
Special Cycles: Controls the action of a device on special cycle operations.
0 — Causes the device to ignore all special cycle operations. State after RST# is logic 0.
1 — Allows the device to monitor special cycle operations.
2BM
Bus Master: Controls the ability of a device to act as a master on the PCI bus.
0 — Disables the device from generating PCI accesses. State after RST# is logic 0.
1 — Allows the device to behave as a bus master.
1MS
Memory Space: Controls the response of a device to memory space accesses.
0 — Disables the device response. State after RST# is logic 0.
1 — Allows the device to respond to memory space accesses.
0
IOS
I/O Space: Controls the response of a device to I/O space accesses.
0 — Disables the device response. State after RST# is logic 0.
1 — Allows the device to respond to I/O space accesses.
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| ISP1564 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller |
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