參數(shù)資料
型號(hào)： ISP1563BM,557
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁數(shù)： 23/102頁
文件大小： 466K
代理商： ISP1563BM,557
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
27 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
8.2.3.2
NEXT_ITEM_PTR register
The Next Item Pointer (NEXT_ITEM_PTR) register describes the location of the next item
in the function’s capability list. The value given is an offset into the function’s PCI
conguration space. If the function does not implement any other capabilities dened by
the PCI-SIG for inclusion in the capabilities list, or if power management is the last item in
the list, then this register must be set to 00h. See Table 33.
8.2.3.3
PMC register
The Power Management Capabilities (PMC) register is a 2-byte register, and the bit
allocation is given in Table 34. This register provides information on the capabilities of the
function related to power management.
[1]
X is 0 for OHCI1 and OHCI2; X is 1 for EHCI.
Table 32.
CAP_ID - Capability Identier register bit description
Address: Value read from address 34h + 0h
Legend: * reset value
Bit
Symbol
Access
Value Description
7 to 0
CAP_ID[7:0]
R
01h*
ID: This eld when 01h identies the linked list item as being PCI power
management registers.
Table 33.
NEXT_ITEM_PTR - Next Item Pointer register bit description
Address: Value read from address 34h + 1h
Legend: * reset value
Bit
Symbol
Access Value Description
7 to 0
NEXT_ITEM_
PTR[7:0]
R
00h*
Next Item Pointer: This eld provides an offset into the function’s PCI
conguration space, pointing to the location of the next item in the function’s
capability list. If there are no additional items in the capabilities list, this register
is set to 00h.
Table 34.
PMC - Power Management Capabilities register bit allocation
Address: Value read from address 34h + 2h
Bit
15
14
13
12
11
10
9
8
Symbol
PME_S[4:0]
D2_S
D1_S
AUX_C
Reset
11
1X[1]
10
Access
RRRRRR
RR
Bit
7
6
5
4
3
2
1
0
Symbol
AUX_C[2:0]
DSI
reserved
PMI
VER[2:0]
Reset
10000010
Access
RRRRRRRR
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