參數(shù)資料
型號： ISP1563BM,557
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁數(shù)： 74/102頁
文件大?。?/td> 466K
代理商： ISP1563BM,557
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
73 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
11.4.3 USBINTR register
The USB Interrupt Enable (USBINTR) register enables and disables reporting of the
corresponding interrupt to the software. When a bit is set and the corresponding interrupt
is active, an interrupt is generated to the host. Interrupt sources that are disabled in this
register still appear in the USBSTS to allow the software to poll for events. The USBSTS
register bit allocation is given in Table 107.
[1]
The reserved bits should always be written with the reset value.
0
USBINT
USB Interrupt: The Host Controller sets this bit on completing a USB transaction, which results
in the retirement of a TD that had its IOC bit set. The Host Controller also sets this bit when a
short packet is detected, that is, the actual number of bytes received was less than the expected
number of bytes. For details, refer to
Enhanced Host Controller Interface Specication for
Universal Serial Bus Rev. 1.0.
Table 106. USBSTS - USB Status register bit description …continued
Address: Content of the base address register + 24h
Bit
Symbol
Description
Table 107. USBINTR - USB Interrupt Enable register bit allocation
Address: Content of the base address register + 28h
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved[1]
IAAE
HSEE
FLRE
PCIE
USBERR
INTE
USBINTE
Reset
00000000
Access
R/W
Table 108. USBINTR - USB Interrupt Enable register bit description
Address: Content of the base address register + 28h
Bit
Symbol
Description
31 to 6
reserved
-
5
IAAE
Interrupt on Asynchronous Advance Enable: When this bit and IAA (bit 5 in the USBSTS
register) are set, the Host Controller issues an interrupt at the next interrupt threshold. The interrupt
is acknowledged by software clearing bit IAA.
4
HSEE
Host System Error Enable: When this bit and HSE (bit 4 in the USBSTS register) are set, the Host
Controller issues an interrupt. The interrupt is acknowledged by software clearing bit HSE.
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