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| 型號： | ISP1563BM,557 |
| 廠商： | ST-ERICSSON |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100 |
| 文件頁數(shù)： | 61/102頁 |
| 文件大?。?/td> | 466K |
| 代理商： | ISP1563BM,557 |
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ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
61 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
11.2 USB legacy support registers
The ISP1563 supports legacy keyboard and mouse. Four operational registers are used
to provide the legacy support. Each of these registers is located on a 32-bit boundary. The
offset of these registers is relative to the base address of the Host Controller operational
registers with HceControl located at offset 100h.
1
PES
On read, Port Enable Status: This bit indicates whether the port is enabled or disabled. The
root hub may clear this bit when an overcurrent condition, disconnect event, switched-off power
or operational bus error is detected. This change also causes Port Enabled Status Change to
be set. The HCD can set this bit by writing Set Port Enable and clear it by writing Clear Port
Enable. This bit cannot be set when CCS (Current Connect Status) is cleared. This bit is also
set on completing a port reset when Reset Status Change is set or on completing a port
suspend when Suspend Status Change is set.
0 — Port is disabled.
1 — Port is enabled.
On write, Set Port Enable: The HCD can set PES (Port Enable Status) by writing logic 1.
Writing logic 0 has no effect. If CCS is cleared, this write does not set PES, but instead sets
CSC (Connect Status Change). This informs the driver that it attempted to enable a
disconnected port.
0
CCS
On read, Current Connect Status: This bit reects the current state of the downstream port.
0 — No device connected.
1 — Device connected.
On write, Clear Port Enable: The HCD can write logic 1 to this bit to clear the PES (Port
Enable Status) bit. Writing logic 0 has no effect. The CCS bit is not affected by any write.
Remark: This bit always reads logic 1 when the attached device is nonremovable
(DeviceRemovable[NDP]).
Table 86.
HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit description …continued
Address: Content of the base address register + 54h
Bit
Symbol
Description
Table 87.
Legacy support registers
Offset
Register
Description
100h
HceControl
used to enable and control the emulation hardware and report various
status information
104h
HceInput
emulation of the legacy Input Buffer register
108h
HceOutput
emulation of the legacy Output Buffer register in which the software writes
keyboard and mouse data
10Ch
HceStatus
emulation of the legacy Status register
Table 88.
Emulated registers
I/O
address
Cycle
type
Register contents
accessed or modied
Side effects
60h
IN
HceOutput
IN from port 60h sets OUT_FULL (bit 0) in HceStatus
to logic 0
60h
OUT
HceInput
OUT to port 60h sets IN_FULL (bit 1) to logic 1 and
CMD_DATA (bit 3) to logic 0 in HceStatus
64h
IN
HceStatus
IN from port 64h returns current value of HceStatus
with no other side effect
64h
OUT
HceInput
OUT to port 64h sets IN_FULL to logic 0 and
CMD_DATA to logic 1 in HceStatus
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