參數(shù)資料
型號： ISP1563BM,557
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁數(shù)： 62/102頁
文件大?。?/td> 466K
代理商： ISP1563BM,557
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
62 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
11.2.1 HceControl register
Table 89 shows the bit allocation of the register.
[1]
The reserved bits should always be written with the reset value.
Table 89.
HceControl - Host Controller Emulation Control register bit allocation
Address: Content of the base address register + 100h
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
A20S
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
IRQ12A
IRQ1A
GA20S
EIRQEN
IRQEN
C_P
EI
EE
Reset
00000000
Access
R/W
R
R/W
Table 90.
HceControl - Host Controller Emulation Control register bit description
Address: Content of the base address register + 100h
Bit
Symbol
Description
31 to 9
reserved
-
8
A20S
A20 State: This bit indicates the current state of gate A20 on the keyboard controller. It is used
to compare against value written to 60h when GA20S is active.
7
IRQ12A
IRQ12 Active: This bit indicates that a positive transition on IRQ12 from the keyboard controller
has occurred.
0 — No effect
1 — Sets IRQ12 to logic 0 (inactive)
6
IRQ1A
IRQ1 Active: This bit indicates that a positive transition on IRQ1 from the keyboard controller
has occurred.
0 — No effect
1 — Sets IRQ11 to logic 0 (inactive)
5
GA20S
Gate A20 Sequence: This bit is set by the Host Controller when a data value of D1h is written
to I/O port 64h and cleared on a write to I/O port 64h of any value other than D1h.
4
EIRQEN
External IRQ Enable: When this bit is set to logic 1, IRQ1 and IRQ12 from the keyboard
controller cause an emulation interrupt. This bit is independent of the setting of the EE bit in this
register.
3
IRQEN
IRQ Enable: When this bit is set, the Host Controller generates IRQ1 or IRQ12 as long as
OUT_FULL (bit 0 in HceStatus) is logic 1. If AUX_OUT_FULL (bit 5 in HceStatus) is logic 0,
then IRQ1 is generated; if it is logic 1, then IRQ12 is generated.
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