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參數(shù)資料
| 型號： | ISP1563BM,557 |
| 廠商： | ST-ERICSSON |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100 |
| 文件頁數(shù)： | 27/102頁 |
| 文件大小： | 466K |
| 代理商： | ISP1563BM,557 |
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ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
30 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
8.2.3.5
PMCSR_BSE register
The PMCSR PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) register supports PCI
bridge-specic functionality and is required for all PCI-to-PCI bridges. The bit allocation of
this register is given in Table 38.
1 to 0
PS[1:0]
Power State: This two-bit eld is used to determine the current power state of the EHCI function and
to set the function into a new power state. The denition of the eld values is given as:
00b — D0
01b — D1
10b — D2
11b — D3hot
If the software attempts to write an unsupported, optional state to this eld, the write operation must
complete normally on the bus; however, the data is discarded and no status change occurs.
Table 37.
PMCSR - Power Management Control/Status register bit description …continued
Address: Value read from address 34h + 4h
Bit
Symbol
Description
Table 38.
PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit allocation
Address: Value read from address 34h + 6h
Bit
7
6
5
4
3
2
1
0
Symbol
BPCC_EN
B2_B3#
reserved
Reset
00000000
Access
RRRRRRRR
Table 39.
PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit description
Address: Value read from address 34h + 6h
Bit
Symbol
Description
7
BPCC_
EN
Bus Power/Clock Control Enable:
1 — Indicates that the bus power or clock control mechanism as dened in Table 40 is enabled.
0 — Indicates that the bus or power control policies as dened in Table 40 are disabled.
When the bus power or clock control mechanism is disabled, the bridge’s PMCSR Power State (PS) eld
cannot be used by the system software to control the power or clock of the bridge’s secondary bus.
6
B2_B3#
B2/B3 support for D3hot: The state of this bit determines the action that is to occur as a direct result of
programming the function to D3hot.
1 — Indicates that when the bridge function is programmed to D3hot, its secondary bus’s PCI clock will
be stopped (B2).
0 — Indicates that when the bridge function is programmed to D3hot, its secondary bus will have its
power removed (B3).
This bit is only meaningful if bit 7 (BPCC_EN) is logic 1.
5 to 0
reserved
-
Table 40.
PCI bus power and clock control
Originating device’s
bridge PM state[1]
Secondary bus
PM state[1]
Resultant actions by bridge (either direct or indirect)
D0
B0
none
D1
B1
none
D2
B2
clock stopped on secondary bus
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