參數(shù)資料
型號: ISP1161ABM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 96/134頁
文件大?。?/td> 587K
代理商: ISP1161ABM
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
96 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13.1.5
DcInterruptEnable register (R/W: C3H/C2H)
This command is used to individually enable or disable interrupts from all endpoints,
as well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT,
suspend, resume, reset). That is, if an interrupt event occurs while the interrupt is not
enabled, nothing will be seen on the interrupt pin. Even if you then enable the
interrupt during the interrupt event, there will still be no interrupt seen on the interrupt
pin, see
Figure 42
.
The DcInterrupt register will not register any interrupt, if it is not already enabled
using the DcInterruptEnable register. The DcInterruptEnable register is not an
Interrupt Mask register.
A bus reset will not change any of the programmed bit values.
The command accesses the DcInterruptEnable register, which consists of 4 bytes.
The bit allocation is given in
Table 84
.
Remark:
For details on interrupt control, see
Section 8.6.3
.
Code (Hex): C2/C3 —
write/read DcInterruptEnable register
Transaction —
write/read 2 words
Pin INT2: HIGH = de-assert; LOW = assert; INTENA = 1.
Fig 42. Interrupt pin waveform.
INT2 pin
interrupt
event
occurs
interrupt
event
occurs
DcInterruptEnable
register
disabled
DcInterruptEnable
register
enabled
interrupt is cleared
004aaa197
Table 84:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DcInterruptEnable register: bit allocation
31
30
29
28
27
26
25
24
reserved
0
0
0
0
0
0
0
0
R/W
23
IEP14
0
R/W
R/W
22
IEP13
0
R/W
R/W
21
IEP12
0
R/W
R/W
20
IEP11
0
R/W
R/W
19
IEP10
0
R/W
R/W
18
IEP9
0
R/W
R/W
17
IEP8
0
R/W
R/W
16
IEP7
0
R/W
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