參數(shù)資料
型號: ISP1161ABM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 95/134頁
文件大?。?/td> 587K
代理商: ISP1161ABM
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
95 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Bit
Symbol
Reset
Access
7
6
5
4
3
2
1
0
DAKOLY
0
R/W
DRQPOL
1
R/W
DAKPOL
0
R/W
EOTPOL
0
R/W
WKUPCS
0
R/W
PWROFF
0
R/W
INTLVL
0
R/W
INTPOL
0
R/W
Table 83:
Bit
15
14
DcHardwareConfiguration register: bit description
Symbol
Description
-
reserved
EXTPUL
Logic 1 indicates that an external 1.5 k
pull-up resistor is used
on pin D
+
and that SoftConnect is not used. Bus reset value:
unchanged.
NOLAZY
Logic 1 disables output on pin CLKOUT of the LazyClock
frequency (100 kHz
±
50 %) during ‘suspend’ state. Logic 0
causes pin CLKOUT to switch to LazyClock output after
approximately 2 ms delay, following the setting of bit GOSUSP
in the DcMode register. Bus reset value: unchanged.
CLKRUN
Logic 1 indicates that the internal clocks are always running,
even during ‘suspend’ state. Logic 0 switches off the internal
oscillator and PLL, when they are not needed. During ‘suspend’
state this bit must be made logic 0 to meet the suspend current
requirements. The clock is stopped after a delay of
approximately 2 ms, following the setting of bit GOSUSP in the
DcMode register. Bus reset value: unchanged.
CLKDIV[3:0]
This field specifies the clock division factor N, which controls the
clock frequency on output CLKOUT. The output frequency in
MHz is given by 48 / (N + 1). The clock frequency range is
3 MHz to 48 MHz (N = 0 to 15). with a reset value of 12 MHz
(N = 3). The hardware design guarantees no glitches during
frequency change. Bus reset value: unchanged.
DAKOLY
Logic 1 selects DACK-only DMA mode. Logic 0 selects
8237 compatible DMA mode. Bus reset value: unchanged.
DRQPOL
Selects DREQ2 pin signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
DAKPOL
Selects DACK2 pin signal polarity (0 = active LOW).
Bus reset value: unchanged.
EOTPOL
Selects EOT pin signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
WKUPCS
Logic 1 enables remote wake-up via a LOW level on input pin
CS (V
BUS
must be present for wake-up on CS).
Bus reset value: unchanged.
PWROFF
Logic 1 enables powering-off during ‘suspend’ state. Output
D_SUSPEND pin is configured as a power switch control signal
for external devices (HIGH during ‘suspend’). This value should
always be initialized to logic 1. Bus reset value: unchanged.
INTLVL
Selects the interrupt signalling mode on output pin INT2
(0 = level, 1 = pulsed). In pulsed mode an interrupt produces an
166 ns pulse. See
Section 8.6.3
for details.
Bus reset value: unchanged.
INTPOL
Selects INT2 pin signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
13
12
11 to 8
7
6
5
4
3
2
1
0
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