參數(shù)資料
型號(hào)： ISP1161ABM
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Full-speed Universal Serial Bus single-chip host and device controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù)： 13/134頁
文件大?。?/td> 587K
代理商： ISP1161ABM
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
13 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Figure 9
shows the DMA interface between a microprocessor system and the
ISP1161A. The ISP1161A provides two DMA channels:
DMA channel 1 (controlled by DREQ1, DACK1 signals) is for the DMA transfer
between a microprocessor’s system memory and ISP1161A HC internal FIFO
buffer RAM
DMA channel 2 (controlled by DREQ2, DACK2 signals) is for the DMA transfer
between a microprocessor system memory and the ISP1161A DC internal FIFO
buffer RAM.
The EOT signal is an external end-of-transfer signal used to terminate the DMA
transfer. Some microprocessors may not have this signal. In this case, the ISP1161A
provides an internal EOT signal to terminate the DMA transfer as well. Setting the
HcDMAConfiguration register (21H - read, A1H - write) enables the ISP1161A HC
internal DMA counter for DMA transfer. When the DMA counter reaches the value set
in the HcTransferCounter register (22H - read, A2H - write), an internal EOT signal
will be generated to terminate the DMA transfer.
8.3 Control register access by PIO mode
8.3.1
I/O port addressing
Table 3
shows the ISP1161A I/O port addressing. Complete decoding of the I/O port
address should include the chip select signal CS and the address lines A1 and A0.
However, the direction of the access of the I/O ports is controlled by the RD and WR
signals. When RD is LOW, the microprocessor reads data from the ISP1161A data
port. When WR is LOW, the microprocessor writes a command to the command port,
or writes data to the data port.
Fig 9.
DMA interface between a microprocessor and an ISP1161A.
004aaa087
D[15:0]
RD
WR
DACK1
DREQ1
EOT
MICRO-
PROCESSOR
ISP1161A
D[15:0]
μ
P bus I/F
RD
WR
DACK1
DREQ1
DACK2
DREQ2
DACK2
DREQ2
EOT
Table 3:
Port
0
1
2
3
I/O port addressing
Pin CS
Pin A1
LOW
LOW
LOW
LOW
LOW
HIGH
LOW
HIGH
Pin A0
LOW
HIGH
LOW
HIGH
Access
R/W
W
R/W
W
Data bus width
16 bits
16 bits
16 bits
16 bits
Description
HC data port
HC command port
DC data port
DC command port
相關(guān)PDF資料
PDF描述
ISP1161 Full-speed Universal Serial Bus single-chip host and device controller
ISP1161A1 Universal Serial Bus single-chip host and device controller
ISP1161A1BD Universal Serial Bus single-chip host and device controller
ISP1161A1BM Universal Serial Bus single-chip host and device controller
ISP1161BD Full-speed Universal Serial Bus single-chip host and device controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1161ABM,518 功能描述:USB 接口集成電路 DO NOT USE ORDER ISP1161A1BM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161ABM,551 功能描述:USB 接口集成電路 DO NOT USE ORDER ISP1161A1BM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161ABM,557 功能描述:USB 接口集成電路 DO NOT USE ORDER ISP1161A1BM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161ABM-S 功能描述:IC USB HOST CTRL FULL-SPD 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1161ABM-T 功能描述:IC USB HOST CTRL FULL-SPD 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
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