參數(shù)資料
型號: IS42S16128-10T
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 256K X 16 SYNCHRONOUS DRAM, 10 ns, PDSO50
封裝: 0.400 INCH, TSOP2-50
文件頁數(shù): 29/75頁
文件大小: 638K
代理商: IS42S16128-10T
IS42S16128
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
29
CAS
latency = 2, 3, burst length = 4
Write Cycle Interruption Using the
Precharge Command
A write cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (t
WDL
) from the precharge command to the
point where burst input is invalid, i.e., the point where input
data is no longer written to device internal memory is zero
clock cycles regardless of the
CAS
.
To inhibit invalid write, the DQM signal must be asserted
HIGH with the precharge command.
This precharge command and burst write command must
be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of dual bank
operation.
Inversely, to write all the burst data to the device, the
precharge command must be executed after the write
data recovery period (t
DPL
) has elapsed. Therefore, the
precharge command must be executed on one clock
cycle that follows the input of the last burst data item.
PRE 0
WRITE A0
COMMAND
DQM
I/O
CLK
D
IN
A0
D
IN
A1
D
IN
A2
D
IN
A3
t
WDL
=0
WRITE (CA=A, BANK 0)
PRECHARGE (BANK 0)
MASKED BY DQM
PRE 0
WRITE A0
COMMAND
I/O
CLK
D
IN
A0
D
IN
A1
D
IN
A2
D
IN
A3
t
DPL
WRITE (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS
Latency
t
WDL
3
0
2
0
t
DPL
1
1
CAS
latency = 2, 3, burst length = 4
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參數(shù)描述
IS42S16128-12T 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S16128-8T 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S16160A-6T 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256 Mb Synchronous DRAM
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