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參數(shù)資料
| 型號： | IS42S16128-10T |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 256K X 16 SYNCHRONOUS DRAM, 10 ns, PDSO50 |
| 封裝： | 0.400 INCH, TSOP2-50 |
| 文件頁數(shù)： | 10/75頁 |
| 文件大?。?/td> | 638K |
| 代理商： | IS42S16128-10T |
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10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
IS42S16128
ISSI
Mode Register Set Command
(
CS
,
RAS
,
CAS
,
WE
= LOW)
The IS42S16128 product incorporates a register that
defines the device operating mode. This command func-
tions as a data input pin that loads this register from the
pins A0 to A9. When power is first applied, the stipulated
power-on sequence should be executed and then the
IS42S16128 should be initialized by executing a mode
register set command.
Note that the mode register set command can be ex-
ecuted only when both banks are in the idle state, i.e..,
deactivated.
Another command cannot be executed after a mode
register set command until after the passage of the period
t
MCD
, which is the period required for mode register set
command execution.
Active Command
(
CS
,
RAS
= LOW,
CAS
,
WE
= HIGH)
The IS42S16128 includes two banks of 512 rows each.
This command selects one of the two banks according to
the A9 pin and activates the row selected by the pins A0
to A8.
This command corresponds to the fall of the
RAS
signal
from HIGH to LOW in conventional DRAMs.
Precharge Command
(
CS
,
RAS
,
WE
= LOW,
CAS
= HIGH)
This command starts precharging the bank selected by
pins A8 and A9. When A8 is HIGH, both banks are
precharged at the same time. When A8 is LOW, the bank
selected by A9 is precharged. After executing this com-
mand, the next command for the selected bank(s) is
executed after passage of the period t
RP
, which is the
period required for bank precharging.
This command corresponds to the
RAS
signal from LOW
to HIGH in conventional DRAMs
Read Command
(
CS
,
CAS
= LOW,
RAS
,
WE
= HIGH)
This command selects the bank specified by the A9 pin
and starts a burst read operation at the start address
specified by pins A0 to A7. Data is output following
CAS
latency.
The selected bank must be activated before executing
this command.
Read Command
(cont.)
When the A8 pin is HIGH, this command functions as a
read with auto-precharge command. After the burst read
completes, the bank selected by pin A9 is precharged.
When the A8 pin is LOW, the bank selected by the A9 pin
remains in the activated state after the burst read com-
pletes.
Write Command
(
CS
,
CAS
,
WE
= LOW,
RAS
= HIGH)
When burst write mode has been selected with the mode
register set command, this command selects the bank
specified by the A9 pin and starts a burst write operation
at the start address specified by pins A0 to A7. This first
data must be input to the I/O pins in the cycle in which this
command.
The selected bank must be activated before executing
this command.
When A8 pin is HIGH, this command functions as a write
with auto-precharge command. After the burst write com-
pletes, the bank selected by pin A9 is precharged. When
the A8 pin is low, the bank selected by the A9 pin remains
in the activated state after the burst write completes.
After the input of the last burst write data, the application
must wait for the write recovery period (t
DPL
, t
DAL
) to
elapse according to
CAS
latency.
Auto-Refresh Command
(
CS
,
RAS
,
CAS
= LOW,
WE
, CKE = HIGH)
This command executes the auto-refresh operation. The
row address and bank to be refreshed are automatically
generated during this operation.
Both banks must be placed in the idle state before
executing this command.
The stipulated period (t
RC
) is required for a single refresh
operation, and no other commands can be executed
during this period.
The device goes to the idle state after the internal refresh
operation completes.
This command must be executed at least 1024 times
every 16 ms.
This command corresponds to CBR auto-refresh in con-
ventional DRAMs.
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PDF描述 |
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| IS42S16128-12T | 128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM |
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| IS42S16160B-7TL | 32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42S16128-12T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16128-8T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16160A-6T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256 Mb Synchronous DRAM |
| IS42S16160A-6TL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256 Mb Synchronous DRAM |
| IS42S16160A-7T | 制造商:Integrated Silicon Solution Inc 功能描述: |
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