參數(shù)資料
型號(hào): IS42S16128-10T
廠(chǎng)商: INTEGRATED SILICON SOLUTION INC
元件分類(lèi): DRAM
英文描述: 128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 256K X 16 SYNCHRONOUS DRAM, 10 ns, PDSO50
封裝: 0.400 INCH, TSOP2-50
文件頁(yè)數(shù): 28/75頁(yè)
文件大?。?/td> 638K
代理商: IS42S16128-10T
28
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
IS42S16128
ISSI
Precharge
The precharge command sets the bank selected by pin A9
to the precharged state. This command can be executed
at a time t
RAS
following the execution of an active com-
mand to the same bank. The selected bank goes to the
idle state at a time t
RP
following the execution of the
precharge command, and an active command can be
executed again for that bank.
If pin A8 is low when this command is executed, the bank
selected by pin A9 will be precharged, and if pin A8 is
HIGH, both banks will be precharged at the same time.
This input to pin A9 is ignored in the latter case.
Read Cycle Interruption
Using the Precharge Command
A read cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (t
RQL
) from the execution of the precharge
command to the completion of the burst output is the clock
cycle of
CAS
latency.
t
RQL
t
RQL
PRE 0
READ A0
COMMAND
I/O
CLK
D
OUT
A0
D
OUT
A1
D
OUT
A2
HI-Z
READ (CA=A, BANK 0)
PRECHARGE (BANK 0)
PRE 0
READ A0
COMMAND
I/O
CLK
D
OUT
A0
D
OUT
A1
D
OUT
A2
HI-Z
READ (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS
Latency
t
RQL
3
3
2
2
CAS
latency = 2, burst length = 4
CAS
latency = 3, burst length = 4
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