參數(shù)資料
型號： IDT82V3280DQG8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 90/171頁
文件大?。?/td> 0K
描述： IC PLL WAN SE STRATUM 2 100-TQFP
標(biāo)準(zhǔn)包裝： 750
類型： 時鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，PECL
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 14:9
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
其它名稱： 82V3280DQG8
IDT82V3280
WAN PLL
Functional Description
25
December 9, 2008
3.6
T0 / T4 DPLL INPUT CLOCK SELECTION
An input clock is selected for T0 DPLL and for T4 DPLL respectively.
For T0 path, the EXT_SW bit and the T0_INPUT_SEL[3:0] bits deter-
mine the input clock selection, as shown in Table 6:
For T4 path, the T4 DPLL may lock to a T0 DPLL output or lock inde-
pendently from T0 path, as determined by the T4_LOCK_T0 bit. When
the T4 DPLL locks to the T0 DPLL output, the T4 selected input clock is
a 77.76 MHz or 8 kHz signal from the T0 DPLL 77.76 MHz path (refer to
Chapter 3.11.5.1 T0 Path), as determined by the T0_FOR_T4 bit. When
the T4 path locks independently from the T0 path, the T4 DPLL input
clock selection is determined by the T4_INPUT_SEL[3:0] bits. Refer to
External Fast selection is done between IN3/IN5 and IN4/IN6 pairs.
Forced selection is done by setting the related registers.
Automatic selection is done based on the results of input clocks qual-
ity monitoring and the related registers configuration.
The selected input clock is attempted to be locked in T0/T4 DPLL.
3.6.1
EXTERNAL FAST SELECTION (T0 ONLY)
The External Fast selection is supported by T0 path only. In External
Fast selection, only IN3/IN5 and IN4/IN6 pairs are available for selec-
tion. Refer to Figure 5. The results of input clocks quality monitoring
clock selection.
The T0 input clock selection is determined by the FF_SRCSW pin
after reset (this pin determines the default value of the EXT_SW bit dur-
ing
reset,
refer
to
the
IN3_SEL_PRIORITY[3:0] bits and the IN4_SEL_PRIORITY[3:0] bits, as
shown in Figure 5 and Table 8:
Figure 5. External Fast Selection
Table 6: Input Clock Selection for T0 Path
Control Bits
Input Clock Selection
EXT_SW
T0_INPUT_SEL[3:0]
1
don’t-care
External Fast selection
0
other than 0000
Forced selection
0000
Automatic selection
Table 7: Input Clock Selection for T4 Path
Control Bits - T4_INPUT_SEL[3:0]
Input Clock Selection
other than 0000
Forced selection
0000
Automatic selection
FF_SRCSW pin
IN3
IN5
IN4
IN6
IN3_SEL_PRIORITY[3:0] bits
IN4_SEL_PRIORITY[3:0] bits
attempted to be
locked in T0 DPLL
Table 8: External Fast Selection
Control Pin & Bits
the Selected Input Clock
FF_SRCSW (after reset)
IN3_SEL_PRIORITY[3:0]
IN4_SEL_PRIORITY[3:0]
high
0000
don’t-care
IN5
other than 0000
IN3
low
don’t-care
0000
IN6
other than 0000
IN4
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