參數(shù)資料
型號: IDT82V3280DQG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 25/171頁
文件大?。?/td> 0K
描述: IC PLL WAN SE STRATUM 2 100-TQFP
標準包裝: 750
類型: 時鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 14:9
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 帶卷 (TR)
其它名稱: 82V3280DQG8
IDT82V3280
WAN PLL
Programming Information
120
December 9, 2008
7.2.6
T0 / T4 DPLL STATE MACHINE CONTROL REGISTERS
OPERATING_STS - DPLL Operating Status
Address: 52H
Type: Read
Default Value: 10000001
Bit
Name
Description
7
EX_SYNC_ALARM_MON
This bit indicates whether the frame sync input signal is in external sync alarm status.
0: No external sync alarm.
1: In external sync alarm status. (default)
6
T4_DPLL_LOCK
This bit indicates the T4 DPLL locking status.
0: Unlocked. (default)
1: Locked.
5
T0_DPLL_SOFT_FREQ_ALARM
This bit indicates whether the T0 DPLL is in soft alarm status.
0: No T0 DPLL soft alarm. (default)
1: In T0 DPLL soft alarm status.
4
T4_DPLL_SOFT_FREQ_ALARM
This bit indicates whether the T4 DPLL is in soft alarm status.
0: No T4 DPLL soft alarm. (default)
1: In T4 DPLL soft alarm status.
3
T0_DPLL_LOCK
This bit indicates the T0 DPLL locking status.
0: Unlocked. (default)
1: Locked.
2 - 0
T0_DPLL_OPERATING_MODE[2:0]
These bits indicate the current operating mode of T0 DPLL.
000: Reserved.
001: Free-Run. (default)
010: Holdover.
011: Reserved.
100: Locked.
101: Pre-Locked2.
110: Pre-Locked.
111: Lost-Phase.
7
6
5
4
3
210
EX_SYNC_ALA
RM_MON
T4_DPLL_LO
CK
T0_DPLL_SOFT
_FREQ_ALARM
T4_DPLL_SOFT
_FREQ_ALARM
T0_DPLL_LO
CK
T0_DPLL_OPER
ATING_MODE2
T0_DPLL_OPER
ATING_MODE1
T0_DPLL_OPER
ATING_MODE0
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